From: Balbir Singh <sblbir@amazon.com>
To: <tglx@linutronix.de>, <mingo@redhat.com>
Cc: <peterz@infradead.org>, <linux-kernel@vger.kernel.org>,
<keescook@chromium.org>, <jpoimboe@redhat.com>,
<tony.luck@intel.com>, <benh@kernel.crashing.org>,
<x86@kernel.org>, <dave.hansen@intel.com>,
<thomas.lendacky@amd.com>, <torvalds@linux-foundation.org>,
Balbir Singh <sblbir@amazon.com>
Subject: [PATCH v3 1/5] x86/mm: change l1d flush runtime prctl behaviour
Date: Fri, 27 Nov 2020 17:59:34 +1100 [thread overview]
Message-ID: <20201127065938.8200-2-sblbir@amazon.com> (raw)
In-Reply-To: <20201127065938.8200-1-sblbir@amazon.com>
Detection of task affinities at API opt-in time is not the best
approach, the approach is to kill the task if it runs on a
SMT enable core. This is better than not flushing the L1D cache
when the task switches from a non-SMT core to an SMT enabled core.
Signed-off-by: Balbir Singh <sblbir@amazon.com>
---
arch/x86/include/asm/processor.h | 2 ++
arch/x86/kernel/smpboot.c | 11 ++++++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 82a08b585818..60dbcdcb833f 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -136,6 +136,8 @@ struct cpuinfo_x86 {
u16 logical_die_id;
/* Index into per_cpu list: */
u16 cpu_index;
+ /* Is SMT active on this core? */
+ bool smt_active;
u32 microcode;
/* Address space bits used by the cache internally */
u8 x86_cache_bits;
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index de776b2e6046..9a94934fae5f 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -635,6 +635,9 @@ void set_cpu_sibling_map(int cpu)
threads = cpumask_weight(topology_sibling_cpumask(cpu));
if (threads > __max_smt_threads)
__max_smt_threads = threads;
+
+ for_each_cpu(i, topology_sibling_cpumask(cpu))
+ cpu_data(i).smt_active = threads > 1;
}
/* maps the cpu to the sched domain representing multi-core */
@@ -1548,10 +1551,16 @@ static void remove_siblinginfo(int cpu)
for_each_cpu(sibling, topology_die_cpumask(cpu))
cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
- for_each_cpu(sibling, topology_sibling_cpumask(cpu))
+
+ for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
+ if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
+ cpu_data(sibling).smt_active = false;
+ }
+
for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
+
cpumask_clear(cpu_llc_shared_mask(cpu));
cpumask_clear(topology_sibling_cpumask(cpu));
cpumask_clear(topology_core_cpumask(cpu));
--
2.17.1
next prev parent reply other threads:[~2020-11-27 7:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 6:59 [PATCH v3 0/5] Next revision of the L1D flush patches Balbir Singh
2020-11-27 6:59 ` Balbir Singh [this message]
2020-12-04 21:07 ` [PATCH v3 1/5] x86/mm: change l1d flush runtime prctl behaviour Thomas Gleixner
2020-12-04 22:44 ` Singh, Balbir
2020-11-27 6:59 ` [PATCH v3 2/5] x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-11-27 6:59 ` [PATCH v3 3/5] x86/mm: Optionally flush L1D on context switch Balbir Singh
2020-12-04 21:21 ` Thomas Gleixner
2020-12-04 22:41 ` Singh, Balbir
2020-11-27 6:59 ` [PATCH v3 4/5] prctl: Hook L1D flushing in via prctl Balbir Singh
2020-12-04 22:19 ` Thomas Gleixner
2020-12-05 2:56 ` Balbir Singh
2020-11-27 6:59 ` [PATCH v3 5/5] Documentation: Add L1D flushing Documentation Balbir Singh
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