| Message ID | 20201127121127.158082-4-manivannan.sadhasivam@linaro.org |
|---|---|
| State | New, archived |
| Headers | show |
| Series |
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| Related | show |
Hi Mani, On 2020-11-27 17:41, Manivannan Sadhasivam wrote: > SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN > register > needs to be written to enable the Write Sub Cache for each SCID. Hence, > use a dedicated "write_scid_en" member with predefined values and write > them for SoCs enabling the "llcc_v2" flag. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/soc/qcom/llcc-qcom.c | 40 ++++++++++++++++++++++++++++++ > include/linux/soc/qcom/llcc-qcom.h | 1 + > 2 files changed, 41 insertions(+) > > diff --git a/drivers/soc/qcom/llcc-qcom.c > b/drivers/soc/qcom/llcc-qcom.c > index 16b421608e9c..3ec4cdffa852 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -47,6 +47,7 @@ > > #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 > #define LLCC_TRP_PCB_ACT 0x21f04 > +#define LLCC_TRP_WRSC_EN 0x21f20 > > #define BANK_OFFSET_STRIDE 0x80000 > > @@ -73,6 +74,7 @@ > * then the ways assigned to this client are not flushed > on power > * collapse. > * @activate_on_init: Activate the slice immediately after it is > programmed > + * @write_scid_en: Bit enables write cache support for a given scid. > */ > struct llcc_slice_config { > u32 usecase_id; > @@ -87,12 +89,14 @@ struct llcc_slice_config { > bool dis_cap_alloc; > bool retain_on_pc; > bool activate_on_init; > + bool write_scid_en; > }; > > struct qcom_llcc_config { > const struct llcc_slice_config *sct_data; > int size; > bool need_llcc_cfg; > + bool llcc_v2; > }; We can extract the version from HW info register and so would not have to maintain a flag for every new version of LLCC. I had a patch to do that which I have sent to you now, perhaps you can check if that works for you and take it with this series? Thanks, Sai
Hi Sai, On Fri, Nov 27, 2020 at 07:09:09PM +0530, Sai Prakash Ranjan wrote: > Hi Mani, > > On 2020-11-27 17:41, Manivannan Sadhasivam wrote: > > SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register > > needs to be written to enable the Write Sub Cache for each SCID. Hence, > > use a dedicated "write_scid_en" member with predefined values and write > > them for SoCs enabling the "llcc_v2" flag. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > drivers/soc/qcom/llcc-qcom.c | 40 ++++++++++++++++++++++++++++++ > > include/linux/soc/qcom/llcc-qcom.h | 1 + > > 2 files changed, 41 insertions(+) > > > > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > > index 16b421608e9c..3ec4cdffa852 100644 > > --- a/drivers/soc/qcom/llcc-qcom.c > > +++ b/drivers/soc/qcom/llcc-qcom.c > > @@ -47,6 +47,7 @@ > > > > #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 > > #define LLCC_TRP_PCB_ACT 0x21f04 > > +#define LLCC_TRP_WRSC_EN 0x21f20 > > > > #define BANK_OFFSET_STRIDE 0x80000 > > > > @@ -73,6 +74,7 @@ > > * then the ways assigned to this client are not flushed > > on power > > * collapse. > > * @activate_on_init: Activate the slice immediately after it is > > programmed > > + * @write_scid_en: Bit enables write cache support for a given scid. > > */ > > struct llcc_slice_config { > > u32 usecase_id; > > @@ -87,12 +89,14 @@ struct llcc_slice_config { > > bool dis_cap_alloc; > > bool retain_on_pc; > > bool activate_on_init; > > + bool write_scid_en; > > }; > > > > struct qcom_llcc_config { > > const struct llcc_slice_config *sct_data; > > int size; > > bool need_llcc_cfg; > > + bool llcc_v2; > > }; > > We can extract the version from HW info register and so > would not have to maintain a flag for every new version > of LLCC. I had a patch to do that which I have sent to you > now, perhaps you can check if that works for you and take > it with this series? > Yeah sure. Will do. Thanks, Mani > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 16b421608e9c..3ec4cdffa852 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -47,6 +47,7 @@ #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 +#define LLCC_TRP_WRSC_EN 0x21f20 #define BANK_OFFSET_STRIDE 0x80000 @@ -73,6 +74,7 @@ * then the ways assigned to this client are not flushed on power * collapse. * @activate_on_init: Activate the slice immediately after it is programmed + * @write_scid_en: Bit enables write cache support for a given scid. */ struct llcc_slice_config { u32 usecase_id; @@ -87,12 +89,14 @@ struct llcc_slice_config { bool dis_cap_alloc; bool retain_on_pc; bool activate_on_init; + bool write_scid_en; }; struct qcom_llcc_config { const struct llcc_slice_config *sct_data; int size; bool need_llcc_cfg; + bool llcc_v2; }; static const struct llcc_slice_config sc7180_data[] = { @@ -147,6 +151,25 @@ static const struct llcc_slice_config sm8150_data[] = { { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, }; +static const struct llcc_slice_config sm8250_data[] = { + { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, + { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), @@ -164,6 +187,12 @@ static const struct qcom_llcc_config sm8150_cfg = { .size = ARRAY_SIZE(sm8150_data), }; +static const struct qcom_llcc_config sm8250_cfg = { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .llcc_v2 = true, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -413,6 +442,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } + if (cfg->llcc_v2) { + u32 wren; + + wren = config->write_scid_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, + BIT(config->slice_id), wren); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -559,6 +598,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 3db6797ba6ff..85f18ae7692f 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -29,6 +29,7 @@ #define LLCC_AUDHW 22 #define LLCC_NPU 23 #define LLCC_WLHW 24 +#define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 #define LLCC_WRCACHE 31
SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register needs to be written to enable the Write Sub Cache for each SCID. Hence, use a dedicated "write_scid_en" member with predefined values and write them for SoCs enabling the "llcc_v2" flag. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/soc/qcom/llcc-qcom.c | 40 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 1 + 2 files changed, 41 insertions(+)