From: Biwen Li <biwen.li@oss.nxp.com>
To: leoyang.li@nxp.com, alexandre.belloni@bootlin.com,
anson.huang@nxp.com, aisheng.dong@nxp.com
Cc: linux-kernel@vger.kernel.org, jiafei.pan@nxp.com,
linux-rtc@vger.kernel.org, Biwen Li <biwen.li@nxp.com>
Subject: [v2 2/2] rtc: pcf2127: clear these flags TSF1, TSF2 before enabling interrupt generation
Date: Wed, 2 Dec 2020 11:18:40 +0800 [thread overview]
Message-ID: <20201202031840.15582-2-biwen.li@oss.nxp.com> (raw)
In-Reply-To: <20201202031840.15582-1-biwen.li@oss.nxp.com>
From: Biwen Li <biwen.li@nxp.com>
Clear these flags TSF1, TSF2 before enabling interrupt generation
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v2:
- clear flag TSF2
drivers/rtc/rtc-pcf2127.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index a5418b657c50..7e3fc70ac5f9 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -659,7 +659,7 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
/*
* Enable timestamp function and store timestamp of first trigger
- * event until TSF1 and TFS2 interrupt flags are cleared.
+ * event until TSF1 and TSF2 interrupt flags are cleared.
*/
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
PCF2127_BIT_TS_CTRL_TSOFF |
@@ -671,6 +671,31 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
return ret;
}
+ /*
+ * Clear TSF1 field of ctrl1 register and TSF2
+ * field of ctrl2 register to clear interrupt
+ * before enabling interrupt generation when
+ * timestamp flag set. Unless the flag TSF1 won't
+ * be cleared and get the interrupt storm.
+ */
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+ PCF2127_BIT_CTRL1_TSF1,
+ 0);
+ if (ret) {
+ dev_err(dev, "%s: control and status register 1 (ctrl1) failed, ret = 0x%x\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
+ PCF2127_BIT_CTRL2_TSF2,
+ 0);
+ if (ret) {
+ dev_err(dev, "%s: control and status register 2 (ctrl2) failed, ret = 0x%x\n",
+ __func__, ret);
+ return ret;
+ }
+
/*
* Enable interrupt generation when TSF1 or TSF2 timestamp flags
* are set. Interrupt signal is an open-drain output and can be
--
2.17.1
next prev parent reply other threads:[~2020-12-02 3:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 3:18 [v2 1/2] rtc: pcf2127: properly set flag WD_CD for rtc chips(pcf2129, pca2129) Biwen Li
2020-12-02 3:18 ` Biwen Li [this message]
2020-12-23 7:06 ` Biwen Li
2021-02-13 21:40 ` (subset) " Alexandre Belloni
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