From: Liu Ying <victor.liu@nxp.com>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org
Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org,
a.hajda@samsung.com, narmstrong@baylibre.com,
Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se,
jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
agx@sigxcpu.org, robert.chiras@nxp.com,
martin.kepplinger@puri.sm
Subject: [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp
Date: Fri, 4 Dec 2020 15:33:43 +0800 [thread overview]
Message-ID: <1607067224-15616-4-git-send-email-victor.liu@nxp.com> (raw)
In-Reply-To: <1607067224-15616-1-git-send-email-victor.liu@nxp.com>
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
index 9b23407..0afce99 100644
--- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
@@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
electrical signals for DSI.
+The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
+in either MIPI-DSI PHY mode or LVDS PHY mode.
+
Required properties:
-- compatible: Must be:
+- compatible: Should be one of:
- "fsl,imx8mq-mipi-dphy"
+ - "fsl,imx8qxp-mipi-dphy"
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
- "phy_ref": phandle and specifier referring to the DPHY ref clock
@@ -14,6 +18,8 @@ Required properties:
- #phy-cells: number of cells in PHY, as defined in
Documentation/devicetree/bindings/phy/phy-bindings.txt
this must be <0>
+- fsl,syscon: Phandle to a system controller, as required by the PHY
+ in i.MX8qxp SoC.
Optional properties:
- power-domains: phandle to power domain
--
2.7.4
next prev parent reply other threads:[~2020-12-04 7:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 7:33 [PATCH 0/4] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2020-12-04 7:33 ` [PATCH 1/4] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() Liu Ying
2020-12-08 9:04 ` Guido Günther
2020-12-15 8:30 ` Guido Günther
2020-12-04 7:33 ` [PATCH 2/4] phy: Add LVDS configuration options Liu Ying
2020-12-08 12:38 ` Laurent Pinchart
2020-12-09 1:20 ` Liu Ying
2020-12-04 7:33 ` Liu Ying [this message]
2020-12-08 9:07 ` [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp Guido Günther
2020-12-08 9:46 ` Liu Ying
2020-12-04 7:33 ` [PATCH 4/4] phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2020-12-08 9:24 ` Guido Günther
2020-12-08 10:03 ` Liu Ying
2020-12-10 7:14 ` Guido Günther
2020-12-10 8:56 ` Liu Ying
2020-12-08 9:02 ` [PATCH 0/4] phy: " Guido Günther
2020-12-08 9:40 ` Liu Ying
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