From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v6 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers
Date: Tue, 22 Dec 2020 21:09:30 +0800 [thread overview]
Message-ID: <1608642587-15634-6-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1608642587-15634-1-git-send-email-weiyi.lu@mediatek.com>
This patch adds the binding documentation of topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks for Mediatek MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 22 ++++++++++++++++++++++
.../bindings/arm/mediatek/mediatek,imgsys.txt | 2 ++
.../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipesys.txt | 1 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
.../bindings/arm/mediatek/mediatek,vdecsys.txt | 8 ++++++++
.../bindings/arm/mediatek/mediatek,vencsys.txt | 1 +
12 files changed, 41 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index ea827e87..551c307 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -18,6 +18,7 @@ Required Properties:
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
+ - "mediatek,mt8192-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index b32d374..699776b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -13,6 +13,7 @@ Required Properties:
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8167-audiosys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
+ - "mediatek,mt8192-audsys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
index a0ce820..7d0b14e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -9,6 +9,10 @@ Required Properties:
- "mediatek,mt6765-camsys", "syscon"
- "mediatek,mt6779-camsys", "syscon"
- "mediatek,mt8183-camsys", "syscon"
+ - "mediatek,mt8192-camsys", "syscon"
+ - "mediatek,mt8192-camsys_rawa", "syscon"
+ - "mediatek,mt8192-camsys_rawb", "syscon"
+ - "mediatek,mt8192-camsys_rawc", "syscon"
- #clock-cells: Must be 1
The camsys controller uses the common clk binding from
@@ -22,3 +26,21 @@ camsys: camsys@1a000000 {
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+
+camsys_rawa: syscon@1a04f000 {
+ compatible = "mediatek,mt8192-camsys_rawa", "syscon";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+};
+
+camsys_rawb: syscon@1a06f000 {
+ compatible = "mediatek,mt8192-camsys_rawb", "syscon";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+};
+
+camsys_rawc: syscon@1a08f000 {
+ compatible = "mediatek,mt8192-camsys_rawc", "syscon";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index dce4c924..b9e599e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -15,6 +15,8 @@ Required Properties:
- "mediatek,mt8167-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- "mediatek,mt8183-imgsys", "syscon"
+ - "mediatek,mt8192-imgsys", "syscon"
+ - "mediatek,mt8192-imgsys2", "syscon"
- #clock-cells: Must be 1
The imgsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index eb3523c..6e05a00 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -19,6 +19,7 @@ Required Properties:
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
+ - "mediatek,mt8192-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
index 2ce889b..9cd1035 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt6779-ipesys", "syscon"
+ - "mediatek,mt8192-ipesys", "syscon"
- #clock-cells: Must be 1
The ipesys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index 054424f..6bfb49a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt6779-mfgcfg", "syscon"
- "mediatek,mt8167-mfgcfg", "syscon"
- "mediatek,mt8183-mfgcfg", "syscon"
+ - "mediatek,mt8192-mfgcfg", "syscon"
- #clock-cells: Must be 1
The mfgcfg controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index d8c9108..81fa345 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
+ - "mediatek,mt8192-mmsys", "syscon"
- #clock-cells: Must be 1
For the clock control, the mmsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index 8723dfe..b405cbc 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -26,6 +26,7 @@ properties:
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
+ - mediatek,mt8192-pericfg
- mediatek,mt8516-pericfg
- const: syscon
- items:
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index 5ce7578..1627e38 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -18,6 +18,7 @@ Required Properties:
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
+ - "mediatek,mt8192-topckgen", "syscon"
- "mediatek,mt8516-topckgen"
- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 9819516..376c82e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -14,6 +14,8 @@ Required Properties:
- "mediatek,mt8167-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- "mediatek,mt8183-vdecsys", "syscon"
+ - "mediatek,mt8192-vdecsys", "syscon"
+ - "mediatek,mt8192-vdecsys_soc", "syscon"
- #clock-cells: Must be 1
The vdecsys controller uses the common clk binding from
@@ -27,3 +29,9 @@ vdecsys: clock-controller@16000000 {
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+
+vdecsys_soc: syscon@1600f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index 6a6a14e..d22de01 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-vencsys", "syscon"
- "mediatek,mt8173-vencsys", "syscon"
- "mediatek,mt8183-vencsys", "syscon"
+ - "mediatek,mt8192-vencsys", "syscon"
- #clock-cells: Must be 1
The vencsys controller uses the common clk binding from
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-12-22 13:11 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 13:09 [PATCH v6 00/22] Mediatek MT8192 clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2021-02-10 12:19 ` Matthias Brugger
2021-02-18 1:40 ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-12-22 13:09 ` Weiyi Lu [this message]
2020-12-22 13:09 ` [PATCH v6 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2021-01-06 10:35 ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2021-01-06 10:37 ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2021-01-06 10:25 ` Ikjoon Jang
2021-01-06 10:42 ` Weiyi Lu
2021-01-06 10:52 ` Ikjoon Jang
2021-01-06 11:06 ` Weiyi Lu
2021-01-07 3:00 ` Ikjoon Jang
2021-02-10 12:46 ` Matthias Brugger
2021-02-18 1:59 ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 11/22] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 12/22] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 13/22] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 15/22] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 16/22] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 17/22] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 18/22] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 19/22] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 20/22] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 21/22] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 22/22] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2021-01-13 7:18 ` [PATCH v6 00/22] Mediatek MT8192 " James Liao
2021-02-09 1:00 ` Stephen Boyd
2021-02-18 1:25 ` Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1608642587-15634-6-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).