From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
Date: Tue, 22 Dec 2020 21:40:14 +0800 [thread overview]
Message-ID: <1608644414-17793-3-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1608644414-17793-1-git-send-email-weiyi.lu@mediatek.com>
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 92dcfbd..ac5dca6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -283,7 +283,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-12-22 13:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 13:40 [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
2020-12-22 13:40 ` [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
2020-12-22 13:40 ` Weiyi Lu [this message]
[not found] ` <4536e0a3-8e64-d2b0-df83-33705d10359a@gmail.com>
2021-02-01 9:31 ` [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
2021-02-01 10:15 ` Matthias Brugger
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