From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: lorenzo.pieralisi@arm.com, robh@kernel.org, linux-pci@vger.kernel.org
Cc: bhelgaas@google.com, linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt lines
Date: Wed, 6 Jan 2021 14:55:40 +0100 [thread overview]
Message-ID: <20210106135540.48420-1-martin.blumenstingl@googlemail.com> (raw)
The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code however
was taking (for example) "13" as raw value instead of taking BIT(13).
Define the legacy PCI interrupt bits using the BIT() macro and then use
these in PCIE_APP_IRN_INT.
Fixes: ed22aaaede44 ("PCI: dwc: intel: PCIe RC controller driver")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/pci/controller/dwc/pcie-intel-gw.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 0cedd1f95f37..ae96bfbb6c83 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -39,6 +39,10 @@
#define PCIE_APP_IRN_PM_TO_ACK BIT(9)
#define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11)
#define PCIE_APP_IRN_BW_MGT BIT(12)
+#define PCIE_APP_IRN_INTA BIT(13)
+#define PCIE_APP_IRN_INTB BIT(14)
+#define PCIE_APP_IRN_INTC BIT(15)
+#define PCIE_APP_IRN_INTD BIT(16)
#define PCIE_APP_IRN_MSG_LTR BIT(18)
#define PCIE_APP_IRN_SYS_ERR_RC BIT(29)
#define PCIE_APP_INTX_OFST 12
@@ -48,10 +52,8 @@
PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
- (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTA) | \
- (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTB) | \
- (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTC) | \
- (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTD))
+ PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
+ PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
#define BUS_IATU_OFFSET SZ_256M
#define RESET_INTERVAL_MS 100
--
2.30.0
next reply other threads:[~2021-01-06 13:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 13:55 Martin Blumenstingl [this message]
2021-03-23 11:35 ` [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt lines Lorenzo Pieralisi
2021-04-08 20:39 ` Martin Blumenstingl
2021-04-09 10:17 ` Rahul Tanwar
2021-04-09 10:29 ` Lorenzo Pieralisi
2021-06-23 13:54 ` Lorenzo Pieralisi
2021-06-23 14:10 ` Lorenzo Pieralisi
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