From: <daire.mcnamara@microchip.com>
To: <cyril.jean@microchip.com>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh+dt@kernel.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.linux.org>,
<padmarao.begari@microchip.com>, <Atish.Patra@wdc.com>,
<mark.rutland@arm.com>, <linux-kernel@vger.kernel.org>,
<palmer@dabbelt.com>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
Subject: [PATCH v2 1/2] dt-bindings: clk: microchip: Add Microchip PolarFire host binding
Date: Thu, 7 Jan 2021 11:34:59 +0000 [thread overview]
Message-ID: <20210107113500.15642-2-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20210107113500.15642-1-daire.mcnamara@microchip.com>
From: Daire McNamara <daire.mcnamara@microchip.com>
Add device tree bindings for the Microchip PolarFire system
clock controller
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
---
.../bindings/clock/microchip,mpfs.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
new file mode 100644
index 000000000000..a4756480a8ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Clock Control Module Binding
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+description: |
+ Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
+ which gates and enables all peripheral clocks.
+
+ This device tree binding describes 32 gate clocks. Clocks are referenced by
+ user nodes by the CLKCFG node phandle and the clock index in the group, from
+ 0 to 31.
+
+properties:
+ compatible:
+ const: microchip,mpfs-clkcfg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+ description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
+ for the full list of PolarFire clock IDs.
+
+ clock-output-names:
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ # Clock Config node:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ref: refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ clock-output-names = "msspllclk";
+ };
+ clkcfg: clock-controller@20002000 {
+ compatible = "microchip,mpfs-clkcfg";
+ reg = <0x0 0x20002000 0x0 0x1000>;
+ clocks = <&ref>;
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "axi", "ahb", "envm", "mac0", "mac1", "mmc", "timer",
+ "mmuart0", "mmuart1", "mmuart2", "mmuart3", "mmuart4",
+ "spi0", "spi1", "i2c0", "i2c1", "can0", "can1", "usb", "rtc",
+ "qspi", "gpio0", "gpio1", "gpio2", "ddrc",
+ "fic0", "fic1", "fic2", "fic3", "athena", "cfm";
+ };
+ };
--
2.25.1
next prev parent reply other threads:[~2021-01-07 11:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 11:34 [PATCH v2 0/2] CLK: microchip: Add clkcfg driver for Microchip PolarFire SoC daire.mcnamara
2021-01-07 11:34 ` daire.mcnamara [this message]
2021-01-07 11:35 ` [PATCH v2 2/2] clk: microchip: Add " daire.mcnamara
2021-01-08 23:46 ` [PATCH v2 0/2] CLK: microchip: Add clkcfg " Atish Patra
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