From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: coresight@lists.linaro.org, mathieu.poirier@linaro.org,
anshuman.khandual@arm.com, mike.leach@linaro.org,
leo.yan@linaro.org, linux-kernel@vger.kernel.org,
jonathan.zhouwen@huawei.com, catalin.marinas@arm.com,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v7 01/28] coresight: etm4x: Handle access to TRCSSPCICRn
Date: Sun, 10 Jan 2021 22:48:23 +0000 [thread overview]
Message-ID: <20210110224850.1880240-2-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210110224850.1880240-1-suzuki.poulose@arm.com>
TRCSSPCICR<n> is present only if all of the following are true:
TRCIDR4.NUMSSCC > n.
TRCIDR4.NUMPC > 0b0000 .
TRCSSCSR<n>.PC == 0b1
Add a helper function to check all the conditions.
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v3:
- Check for TRCSSCSRn.PC too. (Mathieu)
- Moved into a helper for easy reuse.
---
.../coresight/coresight-etm4x-core.c | 29 +++++++++++++++----
drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b20b6ff17cf6..76526679b998 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -59,6 +59,22 @@ static u64 etm4_get_access_type(struct etmv4_config *config);
static enum cpuhp_state hp_online;
+/*
+ * Check if TRCSSPCICRn(i) is implemented for a given instance.
+ *
+ * TRCSSPCICRn is implemented only if :
+ * TRCSSPCICR<n> is present only if all of the following are true:
+ * TRCIDR4.NUMSSCC > n.
+ * TRCIDR4.NUMPC > 0b0000 .
+ * TRCSSCSR<n>.PC == 0b1
+ */
+static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
+{
+ return (n < drvdata->nr_ss_cmp) &&
+ drvdata->nr_pe &&
+ (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
+}
+
static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
{
/* Writing 0 to TRCOSLAR unlocks the trace registers */
@@ -270,8 +286,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
drvdata->base + TRCSSCCRn(i));
writel_relaxed(config->ss_status[i],
drvdata->base + TRCSSCSRn(i));
- writel_relaxed(config->ss_pe_cmp[i],
- drvdata->base + TRCSSPCICRn(i));
+ if (etm4x_sspcicrn_present(drvdata, i))
+ writel_relaxed(config->ss_pe_cmp[i],
+ drvdata->base + TRCSSPCICRn(i));
}
for (i = 0; i < drvdata->nr_addr_cmp; i++) {
writeq_relaxed(config->addr_val[i],
@@ -1324,7 +1341,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
for (i = 0; i < drvdata->nr_ss_cmp; i++) {
state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
- state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
+ if (etm4x_sspcicrn_present(drvdata, i))
+ state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
@@ -1440,8 +1458,9 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
drvdata->base + TRCSSCCRn(i));
writel_relaxed(state->trcsscsr[i],
drvdata->base + TRCSSCSRn(i));
- writel_relaxed(state->trcsspcicr[i],
- drvdata->base + TRCSSPCICRn(i));
+ if (etm4x_sspcicrn_present(drvdata, i))
+ writel_relaxed(state->trcsspcicr[i],
+ drvdata->base + TRCSSPCICRn(i));
}
for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 3dd3e0633328..80e480c7fe5c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -179,6 +179,8 @@
#define TRCSTATR_PMSTABLE_BIT 1
#define ETM_DEFAULT_ADDR_COMP 0
+#define TRCSSCSRn_PC BIT(3)
+
/* PowerDown Control Register bits */
#define TRCPDCR_PU BIT(3)
--
2.24.1
next prev parent reply other threads:[~2021-01-10 22:50 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-10 22:48 [PATCH v7 00/28] coresight: etm4x: Support for system instructions Suzuki K Poulose
2021-01-10 22:48 ` Suzuki K Poulose [this message]
2021-01-10 22:48 ` [PATCH v7 02/28] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2021-01-25 18:39 ` Mathieu Poirier
2021-01-10 22:48 ` [PATCH v7 03/28] coresight: Introduce device access abstraction Suzuki K Poulose
2021-01-25 18:42 ` Mathieu Poirier
2021-01-10 22:48 ` [PATCH v7 04/28] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 05/28] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 06/28] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 07/28] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 08/28] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 09/28] coresight: etm4x: Make offset available for sysfs attributes Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 10/28] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 11/28] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 12/28] coresight: etm4x: Hide sysfs attributes for unavailable registers Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 13/28] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 14/28] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 15/28] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 16/28] coresight: etm4x: Clean up " Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 17/28] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 18/28] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 19/28] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 20/28] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 21/28] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 22/28] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 23/28] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 24/28] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 25/28] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 26/28] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 27/28] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-02-12 10:34 ` Mike Leach
2021-02-12 15:36 ` Suzuki K Poulose
2021-02-12 17:30 ` Mike Leach
2021-02-18 14:51 ` Suzuki K Poulose
2021-01-25 18:49 ` [PATCH v7 00/28] coresight: etm4x: Support for system instructions Mathieu Poirier
2021-01-25 22:05 ` Suzuki K Poulose
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210110224850.1880240-2-suzuki.poulose@arm.com \
--to=suzuki.poulose@arm.com \
--cc=anshuman.khandual@arm.com \
--cc=catalin.marinas@arm.com \
--cc=coresight@lists.linaro.org \
--cc=jonathan.zhouwen@huawei.com \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mathieu.poirier@linaro.org \
--cc=mike.leach@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).