From: Rob Herring <robh@kernel.org>
To: Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@redhat.com>, Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Namhyung Kim <namhyung@kernel.org>,
Raphael Gault <raphael.gault@arm.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ian Rogers <irogers@google.com>,
honnappa.nagarahalli@arm.com,
Itaru Kitayama <itaru.kitayama@gmail.com>
Subject: [PATCH v5 9/9] Documentation: arm64: Document PMU counters access from userspace
Date: Wed, 13 Jan 2021 20:06:05 -0600 [thread overview]
Message-ID: <20210114020605.3943992-10-robh@kernel.org> (raw)
In-Reply-To: <20210114020605.3943992-1-robh@kernel.org>
From: Raphael Gault <raphael.gault@arm.com>
Add a documentation file to describe the access to the pmu hardware
counters from userspace
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
v2:
- Update links to test examples
Changes from Raphael's v4:
- Convert to rSt
- Update chained event status
- Add section for heterogeneous systems
---
Documentation/arm64/index.rst | 1 +
.../arm64/perf_counter_user_access.rst | 56 +++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 Documentation/arm64/perf_counter_user_access.rst
diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
index 97d65ba12a35..eb7b1cabbf08 100644
--- a/Documentation/arm64/index.rst
+++ b/Documentation/arm64/index.rst
@@ -18,6 +18,7 @@ ARM64 Architecture
memory
memory-tagging-extension
perf
+ perf_counter_user_access
pointer-authentication
silicon-errata
sve
diff --git a/Documentation/arm64/perf_counter_user_access.rst b/Documentation/arm64/perf_counter_user_access.rst
new file mode 100644
index 000000000000..e49e141f10cc
--- /dev/null
+++ b/Documentation/arm64/perf_counter_user_access.rst
@@ -0,0 +1,56 @@
+=============================================
+Access to PMU hardware counter from userspace
+=============================================
+
+Overview
+--------
+The perf userspace tool relies on the PMU to monitor events. It offers an
+abstraction layer over the hardware counters since the underlying
+implementation is cpu-dependent.
+Arm64 allows userspace tools to have access to the registers storing the
+hardware counters' values directly.
+
+This targets specifically self-monitoring tasks in order to reduce the overhead
+by directly accessing the registers without having to go through the kernel.
+
+How-to
+------
+The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu
+registers is enabled and that the userspace has access to the relevant
+information in order to use them.
+
+In order to have access to the hardware counter it is necessary to open the event
+using the perf tool interface: the sys_perf_event_open syscall returns a fd which
+can subsequently be used with the mmap syscall in order to retrieve a page of
+memory containing information about the event.
+The PMU driver uses this page to expose to the user the hardware counter's
+index and other necessary data. Using this index enables the user to access the
+PMU registers using the `mrs` instruction.
+
+The userspace access is supported in libperf using the perf_evsel__mmap()
+and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for
+an example.
+
+About heterogeneous systems
+---------------------------
+On heterogeneous systems such as big.LITTLE, userspace PMU counter access can
+only be enabled when the tasks are pinned to a homogeneous subset of cores and
+the corresponding PMU instance is opened by specifying the 'type' attribute.
+The use of generic event types is not supported in this case.
+
+Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It
+can be run using the perf tool to check that the access to the registers works
+correctly from userspace:
+
+.. code-block:: sh
+
+ perf test -v user
+
+About chained events
+--------------------
+Chained events are not supported in userspace. If a 64-bit counter is requested,
+userspace access will only be enabled if the underlying counter is 64-bit.
+
+.. Links
+.. _tools/perf/arch/arm64/tests/user-events.c:
+ https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c
--
2.27.0
next prev parent reply other threads:[~2021-01-14 2:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 2:05 [PATCH v5 0/9] libperf and arm64 userspace counter access support Rob Herring
2021-01-14 2:05 ` [PATCH v5 1/9] arm64: pmu: Add function implementation to update event index in userpage Rob Herring
2021-01-14 2:05 ` [PATCH v5 2/9] arm64: perf: Enable PMU counter direct access for perf event Rob Herring
2021-01-14 2:05 ` [PATCH v5 3/9] tools/include: Add an initial math64.h Rob Herring
2021-01-14 2:06 ` [PATCH v5 4/9] libperf: Add evsel mmap support Rob Herring
2021-01-23 22:42 ` Jiri Olsa
2021-01-14 2:06 ` [PATCH v5 5/9] libperf: tests: Add support for verbose printing Rob Herring
2021-01-14 2:06 ` [PATCH v5 6/9] libperf: Add support for user space counter access Rob Herring
2021-01-14 2:06 ` [PATCH v5 7/9] libperf: Add arm64 support to perf_mmap__read_self() Rob Herring
2021-01-14 2:06 ` [PATCH v5 8/9] perf: arm64: Add test for userspace counter access on heterogeneous systems Rob Herring
2021-01-14 2:06 ` Rob Herring [this message]
2021-02-04 15:18 ` [PATCH v5 0/9] libperf and arm64 userspace counter access support Rob Herring
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