From: Zhang Rui <rui.zhang@intel.com>
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org,
linux-kernel@vger.kernel.org, x86@kernel.org,
kan.liang@linux.intel.com, ak@linux.intel.com
Subject: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
Date: Fri, 15 Jan 2021 17:22:07 +0800 [thread overview]
Message-ID: <20210115092208.20866-2-rui.zhang@intel.com> (raw)
In-Reply-To: <20210115092208.20866-1-rui.zhang@intel.com>
In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the
energy counter, and the higher 32bits are reserved.
Add the MSR mask for these MSRs to fix a problem that the RAPL PMU events
are added erroneously when higher 32bits contain non-zero value.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/rapl.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 7dbbeaacd995..7ed25b2ba05f 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -523,12 +523,15 @@ static bool test_msr(int idx, void *data)
return test_bit(idx, (unsigned long *) data);
}
+/* Only lower 32bits of the MSR represents the energy counter */
+#define RAPL_MSR_MASK 0xFFFFFFFF
+
static struct perf_msr intel_rapl_msrs[] = {
- [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr },
- [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr },
- [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr },
- [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr },
- [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr },
+ [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK },
};
/*
--
2.17.1
next prev parent reply other threads:[~2021-01-15 9:11 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-15 9:22 [PATCH 1/3] perf/x86/rapl: Add msr mask support Zhang Rui
2021-01-15 9:22 ` Zhang Rui [this message]
2021-01-15 20:03 ` [PATCH 2/3] perf/x86/rapl: Fix energy counter detection Peter Zijlstra
2021-01-16 8:19 ` Zhang, Rui
2021-01-16 12:48 ` Peter Zijlstra
2021-01-17 14:44 ` Zhang, Rui
2021-02-03 14:21 ` Peter Zijlstra
2021-01-15 9:22 ` [PATCH 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui
2021-01-16 12:50 ` Peter Zijlstra
2021-01-17 14:33 ` Zhang, Rui
2021-01-25 6:11 ` Zhang, Rui
2021-02-03 14:17 ` Zhang, Rui
2021-02-03 14:47 ` Peter Zijlstra
2021-02-04 16:04 ` Zhang Rui
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