From: JC Kuo <jckuo@nvidia.com>
To: <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<robh@kernel.org>, <jonathanh@nvidia.com>, <kishon@ti.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>
Cc: <linux-tegra@vger.kernel.org>, <linux-usb@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<nkristam@nvidia.com>, <linux-clk@vger.kernel.org>,
JC Kuo <jckuo@nvidia.com>, Thierry Reding <treding@nvidia.com>
Subject: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init
Date: Wed, 20 Jan 2021 15:34:02 +0800 [thread overview]
Message-ID: <20210120073414.69208-3-jckuo@nvidia.com> (raw)
In-Reply-To: <20210120073414.69208-1-jckuo@nvidia.com>
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
v7:
no change
v6:
no change
v5:
no change
v4:
no change
v3:
no change
drivers/clk/tegra/clk-pll.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c5cc0a2dac6f..0193cebe8c5a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
pll_writel(val, PLLE_SS_CTRL, pll);
udelay(1);
- val = pll_readl_misc(pll);
- val &= ~PLLE_MISC_IDDQ_SW_CTRL;
- pll_writel_misc(val, pll);
-
- val = pll_readl(pll->params->aux_reg, pll);
- val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
- val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
- pll_writel(val, pll->params->aux_reg, pll);
- udelay(1);
- val |= PLLE_AUX_SEQ_ENABLE;
- pll_writel(val, pll->params->aux_reg, pll);
-
out:
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
--
2.25.1
next prev parent reply other threads:[~2021-01-20 7:36 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-20 7:34 [PATCH v7 00/14] Tegra XHCI controller ELPG support JC Kuo
2021-01-20 7:34 ` [PATCH v7 01/14] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2021-02-08 19:28 ` Stephen Boyd
2021-01-20 7:34 ` JC Kuo [this message]
2021-02-08 19:28 ` [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init Stephen Boyd
2021-01-20 7:34 ` [PATCH v7 03/14] phy: tegra: xusb: Move usb3 port init for Tegra210 JC Kuo
2021-01-20 7:34 ` [PATCH v7 04/14] phy: tegra: xusb: Rearrange UPHY init on Tegra210 JC Kuo
2021-01-20 7:34 ` [PATCH v7 05/14] phy: tegra: xusb: Add Tegra210 lane_iddq operation JC Kuo
2021-01-20 7:34 ` [PATCH v7 06/14] phy: tegra: xusb: Add sleepwalk and suspend/resume JC Kuo
2021-01-20 7:34 ` [PATCH v7 07/14] soc/tegra: pmc: Provide USB sleepwalk register map JC Kuo
2021-01-20 7:34 ` [PATCH v7 08/14] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2021-01-20 17:35 ` Thierry Reding
2021-01-20 7:34 ` [PATCH v7 09/14] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop JC Kuo
2021-01-20 17:32 ` Thierry Reding
2021-01-20 7:34 ` [PATCH v7 10/14] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 JC Kuo
2021-01-20 7:34 ` [PATCH v7 11/14] phy: tegra: xusb: Tegra210 host mode VBUS control JC Kuo
2021-01-20 7:34 ` [PATCH v7 12/14] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 JC Kuo
2021-01-20 7:34 ` [PATCH v7 13/14] usb: host: xhci-tegra: Unlink power domain devices JC Kuo
2021-01-20 7:34 ` [PATCH v7 14/14] xhci: tegra: Enable ELPG for runtime/system PM JC Kuo
2021-02-05 16:15 ` [PATCH v7 00/14] Tegra XHCI controller ELPG support Thierry Reding
2021-02-05 16:22 ` Greg KH
2021-03-24 12:39 ` Thierry Reding
2021-03-24 13:32 ` Thierry Reding
2021-03-25 6:15 ` Vinod Koul
2021-03-25 14:00 ` Thierry Reding
2021-03-25 14:05 ` Vinod Koul
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