From: JC Kuo <jckuo@nvidia.com>
To: <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<robh@kernel.org>, <jonathanh@nvidia.com>, <kishon@ti.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>
Cc: <linux-tegra@vger.kernel.org>, <linux-usb@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<nkristam@nvidia.com>, <linux-clk@vger.kernel.org>,
JC Kuo <jckuo@nvidia.com>, Thierry Reding <treding@nvidia.com>
Subject: [PATCH v7 05/14] phy: tegra: xusb: Add Tegra210 lane_iddq operation
Date: Wed, 20 Jan 2021 15:34:05 +0800 [thread overview]
Message-ID: <20210120073414.69208-6-jckuo@nvidia.com> (raw)
In-Reply-To: <20210120073414.69208-1-jckuo@nvidia.com>
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
v7:
no change
v6:
no change
v5:
no change
v4:
no change
v3:
add 'misc_ctl2' data member to UPHY lane for carrying MISC_PAD_PX_CTL2 offset
tegra210_uphy_lane_iddq_[enable/disable]() to access 'misc_ctl2' data member
drivers/phy/tegra/xusb-tegra210.c | 82 ++++++++++++++++++++++++++++---
drivers/phy/tegra/xusb.c | 6 +++
drivers/phy/tegra/xusb.h | 6 +++
3 files changed, 86 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index faacb866cd1f..b038d032fea1 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -198,6 +198,18 @@
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
+#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(x) (0x464 + (x) * 0x40)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ BIT(0)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD BIT(1)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK (0x3 << 4)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL (0x3 << 4)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD BIT(24)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ BIT(8)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD BIT(9)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK (0x3 << 12)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL (0x3 << 12)
+#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD BIT(25)
+
#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
@@ -209,6 +221,7 @@
#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
+#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2 0x964
#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
@@ -1640,6 +1653,55 @@ static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
.ops = &tegra210_hsic_ops,
};
+static void tegra210_uphy_lane_iddq_enable(struct tegra_xusb_lane *lane)
+{
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ u32 value;
+
+ value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
+ padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
+}
+
+static void tegra210_uphy_lane_iddq_disable(struct tegra_xusb_lane *lane)
+{
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ u32 value;
+
+ value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
+ value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
+ value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
+ padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
+}
+
+#define TEGRA210_UPHY_LANE(_name, _offset, _shift, _mask, _type, _misc) \
+ { \
+ .name = _name, \
+ .offset = _offset, \
+ .shift = _shift, \
+ .mask = _mask, \
+ .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \
+ .funcs = tegra210_##_type##_functions, \
+ .regs.misc_ctl2 = _misc, \
+ }
+
static const char *tegra210_pcie_functions[] = {
"pcie-x1",
"usb3-ss",
@@ -1648,13 +1710,13 @@ static const char *tegra210_pcie_functions[] = {
};
static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
- TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
- TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
- TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
- TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
- TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
- TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
- TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
+ TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+ TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),
+ TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),
+ TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),
+ TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),
+ TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),
+ TEGRA210_UPHY_LANE("pcie-6", 0x028, 24, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(6)),
};
static struct tegra_xusb_usb3_port *
@@ -1815,6 +1877,8 @@ static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
.probe = tegra210_pcie_lane_probe,
.remove = tegra210_pcie_lane_remove,
+ .iddq_enable = tegra210_uphy_lane_iddq_enable,
+ .iddq_disable = tegra210_uphy_lane_iddq_disable,
};
static int tegra210_pcie_phy_init(struct phy *phy)
@@ -1939,7 +2003,7 @@ static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {
};
static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {
- TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
+ TEGRA210_UPHY_LANE("sata-0", 0x028, 30, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2),
};
static struct tegra_xusb_lane *
@@ -1978,6 +2042,8 @@ static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
.probe = tegra210_sata_lane_probe,
.remove = tegra210_sata_lane_remove,
+ .iddq_enable = tegra210_uphy_lane_iddq_enable,
+ .iddq_disable = tegra210_uphy_lane_iddq_disable,
};
static int tegra210_sata_phy_init(struct phy *phy)
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index 3110aafa8cf6..a34d304677bb 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -321,11 +321,17 @@ static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane)
if (soc->num_funcs < 2)
return;
+ if (lane->pad->ops->iddq_enable)
+ lane->pad->ops->iddq_enable(lane);
+
/* choose function */
value = padctl_readl(padctl, soc->offset);
value &= ~(soc->mask << soc->shift);
value |= lane->function << soc->shift;
padctl_writel(padctl, value, soc->offset);
+
+ if (lane->pad->ops->iddq_disable)
+ lane->pad->ops->iddq_disable(lane);
}
static void tegra_xusb_pad_program(struct tegra_xusb_pad *pad)
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index ccb5dc9b1220..e789d5ff4eb8 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -35,6 +35,10 @@ struct tegra_xusb_lane_soc {
const char * const *funcs;
unsigned int num_funcs;
+
+ struct {
+ unsigned int misc_ctl2;
+ } regs;
};
struct tegra_xusb_lane {
@@ -126,6 +130,8 @@ struct tegra_xusb_lane_ops {
struct device_node *np,
unsigned int index);
void (*remove)(struct tegra_xusb_lane *lane);
+ void (*iddq_enable)(struct tegra_xusb_lane *lane);
+ void (*iddq_disable)(struct tegra_xusb_lane *lane);
};
bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);
--
2.25.1
next prev parent reply other threads:[~2021-01-20 7:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-20 7:34 [PATCH v7 00/14] Tegra XHCI controller ELPG support JC Kuo
2021-01-20 7:34 ` [PATCH v7 01/14] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2021-02-08 19:28 ` Stephen Boyd
2021-01-20 7:34 ` [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init JC Kuo
2021-02-08 19:28 ` Stephen Boyd
2021-01-20 7:34 ` [PATCH v7 03/14] phy: tegra: xusb: Move usb3 port init for Tegra210 JC Kuo
2021-01-20 7:34 ` [PATCH v7 04/14] phy: tegra: xusb: Rearrange UPHY init on Tegra210 JC Kuo
2021-01-20 7:34 ` JC Kuo [this message]
2021-01-20 7:34 ` [PATCH v7 06/14] phy: tegra: xusb: Add sleepwalk and suspend/resume JC Kuo
2021-01-20 7:34 ` [PATCH v7 07/14] soc/tegra: pmc: Provide USB sleepwalk register map JC Kuo
2021-01-20 7:34 ` [PATCH v7 08/14] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2021-01-20 17:35 ` Thierry Reding
2021-01-20 7:34 ` [PATCH v7 09/14] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop JC Kuo
2021-01-20 17:32 ` Thierry Reding
2021-01-20 7:34 ` [PATCH v7 10/14] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 JC Kuo
2021-01-20 7:34 ` [PATCH v7 11/14] phy: tegra: xusb: Tegra210 host mode VBUS control JC Kuo
2021-01-20 7:34 ` [PATCH v7 12/14] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 JC Kuo
2021-01-20 7:34 ` [PATCH v7 13/14] usb: host: xhci-tegra: Unlink power domain devices JC Kuo
2021-01-20 7:34 ` [PATCH v7 14/14] xhci: tegra: Enable ELPG for runtime/system PM JC Kuo
2021-02-05 16:15 ` [PATCH v7 00/14] Tegra XHCI controller ELPG support Thierry Reding
2021-02-05 16:22 ` Greg KH
2021-03-24 12:39 ` Thierry Reding
2021-03-24 13:32 ` Thierry Reding
2021-03-25 6:15 ` Vinod Koul
2021-03-25 14:00 ` Thierry Reding
2021-03-25 14:05 ` Vinod Koul
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