[net,1/1] net: fec: Fix temporary RMII clock reset on link up
diff mbox series

Message ID 20210122151347.30417-2-laurentbadel@eaton.com
State New, archived
Headers show
Series
  • net: fec: Fix RMII clock glitch in FEC
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Commit Message

Badel, Laurent Jan. 22, 2021, 3:13 p.m. UTC
fec_restart() does a hard reset of the MAC module when the link status
changes to up. This temporarily resets the R_CNTRL register which controls
the MII mode of the ENET_OUT clock. In the case of RMII, the clock
frequency momentarily drops from 50MHz to 25MHz until the register is
reconfigured. Some link partners do not tolerate this glitch and
invalidate the link causing failure to establish a stable link when using
PHY polling mode. Since as per IEEE802.11 the criteria for link validity 
are PHY-specific, what the partner should tolerate cannot be assumed, so 
avoid resetting the MII clock by using software reset instead of hardware 
reset when the link is up. This is generally relevant only if the SoC 
provides the clock to an external PHY and the PHY is configured for RMII.

Signed-off-by: Laurent Badel <laurentbadel@eaton.com>
---
 drivers/net/ethernet/freescale/fec.h      | 5 +++++
 drivers/net/ethernet/freescale/fec_main.c | 6 ++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

Comments

Jakub Kicinski Jan. 23, 2021, 1:36 a.m. UTC | #1
On Fri, 22 Jan 2021 16:13:47 +0100 Laurent Badel wrote:
> fec_restart() does a hard reset of the MAC module when the link status
> changes to up. This temporarily resets the R_CNTRL register which controls
> the MII mode of the ENET_OUT clock. In the case of RMII, the clock
> frequency momentarily drops from 50MHz to 25MHz until the register is
> reconfigured. Some link partners do not tolerate this glitch and
> invalidate the link causing failure to establish a stable link when using
> PHY polling mode. Since as per IEEE802.11 the criteria for link validity 
> are PHY-specific, what the partner should tolerate cannot be assumed, so 
> avoid resetting the MII clock by using software reset instead of hardware 
> reset when the link is up. This is generally relevant only if the SoC 
> provides the clock to an external PHY and the PHY is configured for RMII.

>  static const struct fec_devinfo fec_imx6q_info = {
> @@ -953,7 +954,8 @@ fec_restart(struct net_device *ndev)
>  	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
>  	 * instead of reset MAC itself.
>  	 */
> -	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
> +	if (fep->quirks & FEC_QUIRK_HAS_AVB ||
> +	    (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
>  		writel(0, fep->hwp + FEC_ECNTRL);
>  	} else {
>  		writel(1, fep->hwp + FEC_ECNTRL);

drivers/net/ethernet/freescale/fec_main.c: In function ‘fec_restart’:
drivers/net/ethernet/freescale/fec_main.c:958:46: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
  958 |      (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~
Badel, Laurent Jan. 24, 2021, 5:19 p.m. UTC | #2

> drivers/net/ethernet/freescale/fec_main.c: In function ‘fec_restart’:
> drivers/net/ethernet/freescale/fec_main.c:958:46: warning: suggest
> parentheses around ‘&&’ within ‘||’ [-Wparentheses]
>   958 |      (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
>       |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~

Thank you very much for taking the time to review; I'm sorry, I should have caught the warning, I will fix this asap. 

Best regards,

Laurent


-----------------------------
Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la Longeraie 7, 1110, Morges, Switzerland 

-----------------------------

Patch
diff mbox series

diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index c527f4ee1d3a..0602d5d5d2ee 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -462,6 +462,11 @@  struct bufdesc_ex {
  */
 #define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
 
+/* Some link partners do not tolerate the momentary reset of the REF_CLK
+ * frequency when the RNCTL register is cleared by hardware reset.
+ */
+#define FEC_QUIRK_NO_HARD_RESET		(1 << 18)
+
 struct bufdesc_prop {
 	int qid;
 	/* Address of Rx and Tx buffers */
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 04f24c66cf36..280ccea4327f 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -100,7 +100,8 @@  static const struct fec_devinfo fec_imx27_info = {
 static const struct fec_devinfo fec_imx28_info = {
 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
-		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII,
+		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
+		  FEC_QUIRK_NO_HARD_RESET,
 };
 
 static const struct fec_devinfo fec_imx6q_info = {
@@ -953,7 +954,8 @@  fec_restart(struct net_device *ndev)
 	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
 	 * instead of reset MAC itself.
 	 */
-	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
+	if (fep->quirks & FEC_QUIRK_HAS_AVB ||
+	    (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
 		writel(0, fep->hwp + FEC_ECNTRL);
 	} else {
 		writel(1, fep->hwp + FEC_ECNTRL);