From: <stefanc@marvell.com>
To: <netdev@vger.kernel.org>
Cc: <thomas.petazzoni@bootlin.com>, <davem@davemloft.net>,
<nadavh@marvell.com>, <ymarkman@marvell.com>,
<linux-kernel@vger.kernel.org>, <stefanc@marvell.com>,
<kuba@kernel.org>, <linux@armlinux.org.uk>, <mw@semihalf.com>,
<andrew@lunn.ch>, <rmk+kernel@armlinux.org.uk>,
<atenart@kernel.org>
Subject: [PATCH v3 RFC net-next 14/19] net: mvpp2: add ethtool flow control configuration support
Date: Mon, 25 Jan 2021 19:08:01 +0200 [thread overview]
Message-ID: <1611594486-29431-15-git-send-email-stefanc@marvell.com> (raw)
In-Reply-To: <1611594486-29431-1-git-send-email-stefanc@marvell.com>
From: Stefan Chulski <stefanc@marvell.com>
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 98 ++++++++++++++++++++
2 files changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 934d535..1d0d8f2 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -775,6 +775,19 @@
#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
* MSS_RXQ_TRESH_OFFS))
+#define MSS_BUF_POOL_BASE 0x40
+#define MSS_BUF_POOL_OFFS 4
+#define MSS_BUF_POOL_REG(id) (MSS_BUF_POOL_BASE \
+ + (id) * MSS_BUF_POOL_OFFS)
+
+#define MSS_BUF_POOL_STOP_MASK 0xFFF
+#define MSS_BUF_POOL_START_MASK (0xFFF << MSS_BUF_POOL_START_OFFS)
+#define MSS_BUF_POOL_START_OFFS 12
+#define MSS_BUF_POOL_PORTS_MASK (0xF << MSS_BUF_POOL_PORTS_OFFS)
+#define MSS_BUF_POOL_PORTS_OFFS 24
+#define MSS_BUF_POOL_PORT_OFFS(id) (0x1 << \
+ ((id) + MSS_BUF_POOL_PORTS_OFFS))
+
#define MSS_RXQ_TRESH_START_MASK 0xFFFF
#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
#define MSS_RXQ_TRESH_STOP_OFFS 16
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 36e33d5..eab7d12 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -846,6 +846,59 @@ static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
}
+/* Routine disable/enable flow control for BM pool condition */
+static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
+ struct mvpp2_bm_pool *pool,
+ bool en)
+{
+ int val, cm3_state;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
+
+ /* Remove Flow control enable bit to prevent race between FW and Kernel
+ * If Flow control were enabled, it would be re-enabled.
+ */
+ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
+ val &= ~FLOW_CONTROL_ENABLE_BIT;
+ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+ /* Check if BM pool should be enabled/disable */
+ if (en) {
+ /* Set BM pool start and stop thresholds per port */
+ val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+ val |= MSS_BUF_POOL_PORT_OFFS(port->id);
+ val &= ~MSS_BUF_POOL_START_MASK;
+ val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
+ val &= ~MSS_BUF_POOL_STOP_MASK;
+ val |= MSS_THRESHOLD_STOP;
+ mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+ } else {
+ /* Remove BM pool from the port */
+ val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+ val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
+
+ /* Zero BM pool start and stop thresholds to disable pool
+ * flow control if pool empty (not used by any port)
+ */
+ if (!pool->buf_num) {
+ val &= ~MSS_BUF_POOL_START_MASK;
+ val &= ~MSS_BUF_POOL_STOP_MASK;
+ }
+
+ mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+ }
+
+ /* Notify Firmware that Flow control config space ready for update */
+ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
+ val |= cm3_state;
+ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
+}
+
/* Release buffer to BM */
static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
dma_addr_t buf_dma_addr,
@@ -1176,6 +1229,16 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
new_long_pool = MVPP2_BM_LONG;
if (new_long_pool != port->pool_long->id) {
+ if (port->tx_fc) {
+ if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
+ mvpp2_bm_pool_update_fc(port,
+ port->pool_short,
+ false);
+ else
+ mvpp2_bm_pool_update_fc(port, port->pool_long,
+ false);
+ }
+
/* Remove port from old short & long pool */
port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
port->pool_long->pkt_size);
@@ -1193,6 +1256,25 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
mvpp2_swf_bm_pool_init(port);
mvpp2_set_hw_csum(port, new_long_pool);
+
+ if (port->tx_fc) {
+ if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
+ mvpp2_bm_pool_update_fc(port, port->pool_long,
+ true);
+ else
+ mvpp2_bm_pool_update_fc(port, port->pool_short,
+ true);
+ }
+
+ /* Update L4 checksum when jumbo enable/disable on port */
+ if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
+ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+ dev->hw_features &= ~(NETIF_F_IP_CSUM |
+ NETIF_F_IPV6_CSUM);
+ } else {
+ dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+ dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+ }
}
out_set:
@@ -6358,6 +6440,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
{
struct mvpp2_port *port = mvpp2_phylink_to_port(config);
u32 val;
+ int i;
if (mvpp2_is_xlg(interface)) {
if (!phylink_autoneg_inband(mode)) {
@@ -6408,6 +6491,21 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
val);
}
+ if (port->priv->global_tx_fc) {
+ port->tx_fc = tx_pause;
+ if (tx_pause)
+ mvpp2_rxq_enable_fc(port);
+ else
+ mvpp2_rxq_disable_fc(port);
+ if (port->priv->percpu_pools) {
+ for (i = 0; i < port->nrxqs; i++)
+ mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
+ } else {
+ mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
+ mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
+ }
+ }
+
mvpp2_port_enable(port);
mvpp2_egress_enable(port);
--
1.9.1
next prev parent reply other threads:[~2021-01-25 17:17 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 17:07 [PATCH v3 RFC net-next 00/19] net: mvpp2: Add TX Flow Control support stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 01/19] doc: marvell: add cm3-mem device tree bindings description stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 02/19] dts: marvell: add CM3 SRAM memory to cp115 ethernet device tree stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 03/19] net: mvpp2: add CM3 SRAM memory map stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 04/19] doc: marvell: add PPv2.3 description to marvell-pp2.txt stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 05/19] net: mvpp2: add PPv23 version definition stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 06/19] net: mvpp2: always compare hw-version vs MVPP21 stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 07/19] net: mvpp2: increase BM pool size to 2048 buffers stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 08/19] net: mvpp2: increase RXQ size to 1024 descriptors stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 09/19] net: mvpp2: add FCA periodic timer configurations stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 10/19] net: mvpp2: add FCA RXQ non occupied descriptor threshold stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 11/19] net: mvpp2: add spinlock for FW FCA configuration path stefanc
2021-01-25 17:07 ` [PATCH v3 RFC net-next 12/19] net: mvpp2: enable global flow control stefanc
2021-01-25 17:08 ` [PATCH v3 RFC net-next 13/19] net: mvpp2: add RXQ flow control configurations stefanc
2021-01-25 17:08 ` stefanc [this message]
2021-01-25 17:08 ` [PATCH v3 RFC net-next 15/19] net: mvpp2: add BM protection underrun feature support stefanc
2021-01-25 17:08 ` [PATCH v3 RFC net-next 16/19] net: mvpp2: add PPv23 RX FIFO flow control stefanc
2021-01-25 17:08 ` [PATCH v3 RFC net-next 17/19] net: mvpp2: set 802.3x GoP Flow Control mode stefanc
2021-01-25 17:08 ` [PATCH v3 RFC net-next 18/19] net: mvpp2: limit minimum ring size to 1024 descriptors stefanc
2021-01-25 17:08 ` [PATCH v3 RFC net-next 19/19] net: mvpp2: add TX FC firmware check stefanc
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