From: Nathan Fontenot <nathan.fontenot@amd.com>
To: rrichter@amd.com, shuah@kernel.org, linux-kernel@vger.kernel.org,
trenn@suse.com, linux-pm@vger.kernel.org
Cc: boris.ostrovsky@oracle.com, joao.m.martins@oracle.com,
konrad.wilk@oracle.com
Subject: [PATCH v2 1/8] cpupower: Update msr_pstate union struct naming
Date: Mon, 25 Jan 2021 11:34:36 -0600 [thread overview]
Message-ID: <161159607626.68367.14656572319107224636.stgit@ethanol01c7-host.amd.com> (raw)
In-Reply-To: <161159600371.68367.14890273216040482793.stgit@ethanol01c7-host.amd.com>
The msr_pstate union struct named fam17h_bits is misleading since
this is the struct to use for all families >= 0x17, not just
for family 0x17. Rename the bits structs to be 'pstate' (for pre
family 17h CPUs) and 'pstatedef' (for CPUs since fam 17h) to align
closer with PPR/BDKG (1) naming.
There are no functional changes as part of this update.
1: AMD Processor Programming Reference (PPR) and BIOS and
Kernel Developer's Guide (BKDG) available at:
http://developer.amd.com/resources/developer-guides-manuals
Signed-off-by: Nathan Fontenot <nathan.fontenot@amd.com>
---
Updates for v2: Add links to PPR/BKDG in commit message
---
tools/power/cpupower/utils/helpers/amd.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c
index 7c4f83a8c973..34368436bbd6 100644
--- a/tools/power/cpupower/utils/helpers/amd.c
+++ b/tools/power/cpupower/utils/helpers/amd.c
@@ -13,7 +13,8 @@
#define MSR_AMD_PSTATE 0xc0010064
#define MSR_AMD_PSTATE_LIMIT 0xc0010061
-union msr_pstate {
+union core_pstate {
+ /* pre fam 17h: */
struct {
unsigned fid:6;
unsigned did:3;
@@ -26,7 +27,8 @@ union msr_pstate {
unsigned idddiv:2;
unsigned res3:21;
unsigned en:1;
- } bits;
+ } pstate;
+ /* since fam 17h: */
struct {
unsigned fid:8;
unsigned did:6;
@@ -35,36 +37,36 @@ union msr_pstate {
unsigned idddiv:2;
unsigned res1:31;
unsigned en:1;
- } fam17h_bits;
+ } pstatedef;
unsigned long long val;
};
-static int get_did(int family, union msr_pstate pstate)
+static int get_did(int family, union core_pstate pstate)
{
int t;
if (family == 0x12)
t = pstate.val & 0xf;
else if (family == 0x17 || family == 0x18)
- t = pstate.fam17h_bits.did;
+ t = pstate.pstatedef.did;
else
- t = pstate.bits.did;
+ t = pstate.pstate.did;
return t;
}
-static int get_cof(int family, union msr_pstate pstate)
+static int get_cof(int family, union core_pstate pstate)
{
int t;
int fid, did, cof;
did = get_did(family, pstate);
if (family == 0x17 || family == 0x18) {
- fid = pstate.fam17h_bits.fid;
+ fid = pstate.pstatedef.fid;
cof = 200 * fid / did;
} else {
t = 0x10;
- fid = pstate.bits.fid;
+ fid = pstate.pstate.fid;
if (family == 0x11)
t = 0x8;
cof = (100 * (fid + t)) >> did;
@@ -89,7 +91,7 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family,
int boost_states, unsigned long *pstates, int *no)
{
int i, psmax, pscur;
- union msr_pstate pstate;
+ union core_pstate pstate;
unsigned long long val;
/* Only read out frequencies from HW when CPU might be boostable
@@ -119,9 +121,9 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family,
}
if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val))
return -1;
- if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en))
+ if ((cpu_family == 0x17) && (!pstate.pstatedef.en))
continue;
- else if (!pstate.bits.en)
+ else if (!pstate.pstate.en)
continue;
pstates[i] = get_cof(cpu_family, pstate);
next prev parent reply other threads:[~2021-01-25 17:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 17:34 [PATCH v2 0/8] cpupower: Updates and cleanup to support AMD Family 0x19 Nathan Fontenot
2021-01-25 17:34 ` Nathan Fontenot [this message]
2021-01-25 17:34 ` [PATCH v2 2/8] cpupower: Correct macro name for CPB caps flag Nathan Fontenot
2021-01-25 17:34 ` [PATCH v2 3/8] cpupower: Add CPUPOWER_CAP_AMD_HW_PSTATE cpuid " Nathan Fontenot
2021-01-25 17:35 ` [PATCH v2 4/8] cpupower: Remove unused pscur variable Nathan Fontenot
2021-01-25 17:35 ` [PATCH v2 5/8] cpupower: Update family checks when decoding HW pstates Nathan Fontenot
2021-01-25 17:35 ` [PATCH v2 6/8] cpupower: Condense pstate enabled bit checks in decode_pstates() Nathan Fontenot
2021-01-25 17:36 ` [PATCH v2 7/8] cpupower: Remove family arg to decode_pstates() Nathan Fontenot
2021-01-25 17:36 ` [PATCH v2 8/8] cpupower: Add cpuid cap flag for MSR_AMD_HWCR support Nathan Fontenot
2021-01-26 16:45 ` [PATCH v2 0/8] cpupower: Updates and cleanup to support AMD Family 0x19 Shuah Khan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=161159607626.68367.14656572319107224636.stgit@ethanol01c7-host.amd.com \
--to=nathan.fontenot@amd.com \
--cc=boris.ostrovsky@oracle.com \
--cc=joao.m.martins@oracle.com \
--cc=konrad.wilk@oracle.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rrichter@amd.com \
--cc=shuah@kernel.org \
--cc=trenn@suse.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).