From: Zhang Rui <rui.zhang@intel.com>
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org,
linux-kernel@vger.kernel.org, x86@kernel.org,
kan.liang@linux.intel.com, ak@linux.intel.com
Subject: [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters
Date: Fri, 5 Feb 2021 00:18:15 +0800 [thread overview]
Message-ID: <20210204161816.12649-2-rui.zhang@intel.com> (raw)
In-Reply-To: <20210204161816.12649-1-rui.zhang@intel.com>
In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the energy
counter.
On previous platforms, the higher 32bits are reverved and always return
Zero. But on Intel SapphireRapids platform, the higher 32bits are reused
for other purpose and return non-zero value.
Thus check the lower 32bits only for these ENERGY_COUTNER MSRs, to make
sure the RAPL PMU events are not added erroneously when higher 32bits
contain non-zero value.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/rapl.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 7dbbeaacd995..7ed25b2ba05f 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -523,12 +523,15 @@ static bool test_msr(int idx, void *data)
return test_bit(idx, (unsigned long *) data);
}
+/* Only lower 32bits of the MSR represents the energy counter */
+#define RAPL_MSR_MASK 0xFFFFFFFF
+
static struct perf_msr intel_rapl_msrs[] = {
- [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr },
- [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr },
- [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr },
- [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr },
- [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr },
+ [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK },
+ [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK },
};
/*
--
2.17.1
next prev parent reply other threads:[~2021-02-04 16:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-04 16:18 [PATCH V2 1/3] perf/x86/rapl: Add msr mask support Zhang Rui
2021-02-04 16:18 ` Zhang Rui [this message]
2021-02-10 13:59 ` [tip: perf/core] perf/x86/rapl: Only check lower 32bits for RAPL energy counters tip-bot2 for Zhang Rui
2021-02-04 16:18 ` [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui
2021-02-10 13:59 ` [tip: perf/core] " tip-bot2 for Zhang Rui
2021-02-10 13:59 ` [tip: perf/core] perf/x86/rapl: Add msr mask support tip-bot2 for Zhang Rui
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