From: Vinod Koul <vkoul@kernel.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
Andy Gross <agross@kernel.org>,
linux-kernel@vger.kernel.org
Subject: [PATCH 7/6] arm64: dts: qcom: sm8350: Add cpufreq node
Date: Tue, 16 Feb 2021 16:47:03 +0530 [thread overview]
Message-ID: <20210216111703.1838663-1-vkoul@kernel.org> (raw)
In-Reply-To: <20210212115532.1339942-8-vkoul@kernel.org>
Add cpufreq node and reference it for the CPUs.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
- appended this to dts patch series
arch/arm64/boot/dts/qcom/sm8350.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 1aa2a9e00a75..91d4cbbe38dc 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -60,6 +61,7 @@ CPU1: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -72,6 +74,7 @@ CPU2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -84,6 +87,7 @@ CPU3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -96,6 +100,7 @@ CPU4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -108,6 +113,7 @@ CPU5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -121,6 +127,7 @@ CPU6: cpu@600 {
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +140,7 @@ CPU7: cpu@700 {
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -852,6 +860,19 @@ apps_bcm_voter: bcm_voter {
};
};
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.26.2
prev parent reply other threads:[~2021-02-16 11:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 11:55 [PATCH 0/7] arm64: dts: qcom: sm8350: additional device support Vinod Koul
2021-02-12 11:55 ` [PATCH 1/7] arm64: dts: qcom: sm8350: fix typo Vinod Koul
2021-02-12 11:55 ` [PATCH 2/7] arm64: dts: qcom: sm8350: Add rpmhpd node Vinod Koul
2021-02-12 11:55 ` [PATCH 3/7] arm64: dts: qcom: sm8350: Add rmtfs node Vinod Koul
2021-02-12 11:55 ` [PATCH 4/7] arm64: dts: qcom: sm8350: Add SMP2P nodes Vinod Koul
2021-02-12 11:55 ` [PATCH 5/7] arm64: dts: qcom: sm8350: Add remoteprocs Vinod Koul
2021-02-12 11:55 ` [PATCH 6/7] arm64: dts: qcom: sm8350-mtp: Enable remoteprocs Vinod Koul
2021-02-12 11:55 ` [PATCH 7/7] arm64: dts: qcom: sm8350: Use enums for GCC Vinod Koul
2021-02-16 11:17 ` Vinod Koul [this message]
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