linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
	mike.leach@linaro.org, anshuman.khandual@arm.com,
	leo.yan@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
	Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers
Date: Thu, 25 Feb 2021 19:35:27 +0000	[thread overview]
Message-ID: <20210225193543.2920532-4-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210225193543.2920532-1-suzuki.poulose@arm.com>

Currently we advertise the ID_AA6DFR0_EL1.TRACEVER for the guest,
when the trace register accesses are trapped (CPTR_EL2.TTA == 1).
So, the guest will get an undefined instruction, if trusts the
ID registers and access one of the trace registers.
Lets be nice to the guest and hide the feature to avoid
unexpected behavior.

Even though this can be done at KVM sysreg emulation layer,
we do this by removing the TRACEVER from the sanitised feature
register field. This is fine as long as the ETM drivers
can handle the individual trace units separately, even
when there are differences among the CPUs.

Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
New patch
---
 arch/arm64/kernel/cpufeature.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 066030717a4c..a4698f09bf32 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -383,7 +383,6 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 	 * of support.
 	 */
 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 	ARM64_FTR_END,
 };
-- 
2.24.1


  parent reply	other threads:[~2021-02-25 19:41 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25 19:35 [PATCH v4 00/19] arm64: coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 01/19] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 02/19] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-03-16 17:04   ` Mathieu Poirier
2021-03-22 12:29     ` Suzuki K Poulose
2021-02-25 19:35 ` Suzuki K Poulose [this message]
2021-03-22 22:21   ` [PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 04/19] kvm: arm64: nvhe: Save the SPE context early Suzuki K Poulose
2021-03-01 16:32   ` Alexandru Elisei
2021-03-02 10:01     ` Suzuki K Poulose
2021-03-02 10:13       ` Marc Zyngier
2021-03-02 11:00       ` Alexandru Elisei
2021-02-25 19:35 ` [PATCH v4 05/19] kvm: arm64: Disable guest access to trace filter controls Suzuki K Poulose
2021-03-22 22:24   ` Suzuki K Poulose
2021-03-23  9:16     ` Marc Zyngier
2021-03-23  9:44       ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 06/19] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 07/19] arm64: Add TRBE definitions Suzuki K Poulose
2021-03-16 17:46   ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 08/19] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-03-16 17:49   ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 09/19] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-16 19:30   ` Mathieu Poirier
2021-03-17 10:44     ` Suzuki K Poulose
2021-03-17 17:09       ` Mathieu Poirier
2021-03-22 21:28   ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-16 20:23   ` Mathieu Poirier
2021-03-17 10:47     ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 11/19] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 12/19] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 13/19] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose
2021-02-25 22:33   ` kernel test robot
2021-02-26  6:25   ` kernel test robot
2021-02-25 19:35 ` [PATCH v4 14/19] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 15/19] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-03-06 21:06   ` Rob Herring
2021-03-08 17:25     ` Mike Leach
2021-03-22 16:53     ` Suzuki K Poulose
2021-03-22 17:28       ` Rob Herring
2021-03-22 22:49         ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 16/19] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 17/19] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-02-26  6:34   ` kernel test robot
2021-03-01 13:54     ` Suzuki K Poulose
2021-03-02 10:21       ` Anshuman Khandual
2021-03-01 14:08   ` [PATCH v4.1 " Suzuki K Poulose
2021-03-08 17:26   ` [PATCH v4 " Mike Leach
2021-03-22 16:57     ` Suzuki K Poulose
2021-03-17 19:31   ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 18/19] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-03-08 17:26   ` Mike Leach
2021-03-19 10:30     ` Suzuki K Poulose
2021-03-19 11:55       ` Mike Leach
2021-03-22 21:24         ` Mathieu Poirier
2021-03-22 23:00           ` Suzuki K Poulose
2021-03-18 18:08   ` Mathieu Poirier
2021-03-19 10:34     ` Suzuki K Poulose
2021-03-19 14:47       ` Mathieu Poirier
2021-03-19 17:58   ` Mathieu Poirier
2021-03-22 21:20   ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 19/19] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210225193543.2920532-4-suzuki.poulose@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=anshuman.khandual@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mathieu.poirier@linaro.org \
    --cc=maz@kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).