From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com,
ezequiel@collabora.com, mchehab@kernel.org,
gregkh@linuxfoundation.org
Cc: kernel@pengutronix.de, linux-imx@nxp.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org,
kernel@collabora.com, benjamin.gaignard@collabora.com
Subject: [PATCH v2 1/5] dt-bindings: reset: IMX8MQ VPU reset
Date: Fri, 26 Feb 2021 10:11:24 +0100 [thread overview]
Message-ID: <20210226091128.14379-2-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com>
Document bindings for IMX8MQ VPU reset hardware block
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
.../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++
include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++
2 files changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml
create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml
new file mode 100644
index 000000000000..00020421c0e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MQ VPU Reset Controller
+
+maintainers:
+ - Benjamin Gaignard <benjamin.gaignard@collabora.com>
+
+description: |
+ The VPU reset controller is used to reset the video processor
+ unit peripherals. Device nodes that need access to reset lines should
+ specify them as a reset phandle in their corresponding node as
+ specified in reset.txt.
+
+ For list of all valid reset indices see
+ <dt-bindings/reset/imx8mq-vpu-reset.h> for i.MX8MQ.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mq-vpu-reset
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mq-clock.h>
+
+ vpu-reset@38320000 {
+ compatible = "fsl,imx8mq-vpu-reset", "syscon";
+ reg = <0x38320000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h
new file mode 100644
index 000000000000..efcbe18177fe
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, Collabora
+ *
+ * i.MX7 System Reset Controller (SRC) driver
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ
+#define DT_BINDINGS_VPU_RESET_IMX8MQ
+
+#define IMX8MQ_RESET_VPU_RESET_G1 0
+#define IMX8MQ_RESET_VPU_RESET_G2 1
+
+#endif
--
2.25.1
next prev parent reply other threads:[~2021-02-26 9:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 9:11 [PATCH v2 0/5] Reset driver for IMX8MQ VPU hardware block Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard [this message]
2021-02-26 9:11 ` [PATCH v2 2/5] dt-bindings: media: IMX8MQ VPU: document reset usage Benjamin Gaignard
2021-03-01 14:44 ` Rob Herring
2021-02-26 9:11 ` [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 4/5] media: hantro: Use reset driver Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 5/5] arm64: dts: imx8mq: Use reset driver for VPU hardware block Benjamin Gaignard
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