From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: vkoul@kernel.org
Cc: kishon@ti.com, linux-phy@lists.infradead.org,
devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org,
neil@brown.name
Subject: [PATCH] phy: ralink: phy-mt7621-pci: fix XTAL bitmask
Date: Tue, 2 Mar 2021 11:54:12 +0100 [thread overview]
Message-ID: <20210302105412.16221-1-sergio.paracuellos@gmail.com> (raw)
When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.
Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/phy/ralink/phy-mt7621-pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c
index 9a610b414b1f..84ee2b5c2228 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -62,7 +62,7 @@
#define RG_PE1_FRC_MSTCKDIV BIT(5)
-#define XTAL_MASK GENMASK(7, 6)
+#define XTAL_MASK GENMASK(8, 6)
#define MAX_PHYS 2
--
2.25.1
next reply other threads:[~2021-03-02 11:13 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-02 10:54 Sergio Paracuellos [this message]
2021-03-02 12:28 ` [PATCH] phy: ralink: phy-mt7621-pci: fix XTAL bitmask Vinod Koul
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