From: Paul Cercueil <paul@crapouillou.net>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Zhou Yanjie <zhouyanjie@wanyeetech.com>
Cc: od@zcrc.me, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH 3/6] clk: ingenic: Read bypass register only when there is one
Date: Sun, 7 Mar 2021 14:17:56 +0000 [thread overview]
Message-ID: <20210307141759.30426-4-paul@crapouillou.net> (raw)
In-Reply-To: <20210307141759.30426-1-paul@crapouillou.net>
Rework the clock code so that the bypass register is only read when
there is actually a bypass functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/clk/ingenic/cgu.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 0619d45a950c..7686072aff8f 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
od_enc = ctl >> pll_info->od_shift;
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
- ctl = readl(cgu->base + pll_info->bypass_reg);
+ if (!pll_info->no_bypass_bit) {
+ ctl = readl(cgu->base + pll_info->bypass_reg);
- bypass = !pll_info->no_bypass_bit &&
- !!(ctl & BIT(pll_info->bypass_bit));
+ bypass = !!(ctl & BIT(pll_info->bypass_bit));
- if (bypass)
- return parent_rate;
+ if (bypass)
+ return parent_rate;
+ }
for (od = 0; od < pll_info->od_max; od++) {
if (pll_info->od_encoding[od] == od_enc)
@@ -225,11 +226,13 @@ static int ingenic_pll_enable(struct clk_hw *hw)
u32 ctl;
spin_lock_irqsave(&cgu->lock, flags);
- ctl = readl(cgu->base + pll_info->bypass_reg);
+ if (!pll_info->no_bypass_bit) {
+ ctl = readl(cgu->base + pll_info->bypass_reg);
- ctl &= ~BIT(pll_info->bypass_bit);
+ ctl &= ~BIT(pll_info->bypass_bit);
- writel(ctl, cgu->base + pll_info->bypass_reg);
+ writel(ctl, cgu->base + pll_info->bypass_reg);
+ }
ctl = readl(cgu->base + pll_info->reg);
--
2.30.1
next prev parent reply other threads:[~2021-03-07 14:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-07 14:17 [PATCH 0/6] clk: Ingenic JZ4760(B) support Paul Cercueil
2021-03-07 14:17 ` [PATCH 1/6] dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles Paul Cercueil
2021-03-08 22:56 ` Rob Herring
2021-03-07 14:17 ` [PATCH 2/6] clk: Support bypassing dividers Paul Cercueil
2021-03-07 14:17 ` Paul Cercueil [this message]
2021-03-07 14:17 ` [PATCH 4/6] clk: ingenic: Remove pll_info.no_bypass_bit Paul Cercueil
2021-03-07 14:17 ` [PATCH 5/6] clk: ingenic: Support overriding PLLs M/N/OD calc algorithm Paul Cercueil
2021-03-10 14:42 ` Zhou Yanjie
2021-03-07 14:17 ` [PATCH 6/6] clk: ingenic: Add support for the JZ4760 Paul Cercueil
2021-03-17 12:41 ` Zhou Yanjie
2021-03-22 17:40 ` Paul Cercueil
2021-03-23 15:41 ` Zhou Yanjie
2021-03-23 15:55 ` Paul Cercueil
2021-03-09 6:31 ` [PATCH 0/6] clk: Ingenic JZ4760(B) support Zhou Yanjie
2021-03-09 15:33 ` Zhou Yanjie
2021-03-10 14:40 ` Zhou Yanjie
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