[v2,6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
diff mbox series

Message ID 17994571deaf703e65ece7e44c742f82c988cf39.1615954046.git.greentime.hu@sifive.com
State New, archived
Headers show
Series
  • Add SiFive FU740 PCIe host controller driver support
Related show

Commit Message

Greentime Hu March 18, 2021, 6:08 a.m. UTC
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Palmer Dabbelt March 31, 2021, 12:24 a.m. UTC | #1
On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime.hu@sifive.com wrote:
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> index d1bb22b11920..d0839739b425 100644
> --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -158,6 +158,7 @@ prci: clock-controller@10000000 {
>  			reg = <0x0 0x10000000 0x0 0x1000>;
>  			clocks = <&hfclk>, <&rtcclk>;
>  			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  		uart0: serial@10010000 {
>  			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> @@ -288,5 +289,38 @@ gpio: gpio@10060000 {
>  			clocks = <&prci PRCI_CLK_PCLK>;
>  			status = "disabled";
>  		};
> +		pcie@e00000000 {
> +			#address-cells = <3>;
> +			#interrupt-cells = <1>;
> +			#num-lanes = <8>;
> +			#size-cells = <2>;
> +			compatible = "sifive,fu740-pcie";
> +			reg = <0xe 0x00000000 0x1 0x0
> +			       0xd 0xf0000000 0x0 0x10000000
> +			       0x0 0x100d0000 0x0 0x1000>;
> +			reg-names = "dbi", "config", "mgmt";
> +			device_type = "pci";
> +			dma-coherent;
> +			bus-range = <0x0 0xff>;
> +			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
> +				  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
> +				  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
> +				  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
> +			num-lanes = <0x8>;
> +			interrupts = <56 57 58 59 60 61 62 63 64>;
> +			interrupt-names = "msi", "inta", "intb", "intc", "intd";
> +			interrupt-parent = <&plic0>;
> +			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> +			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> +					<0x0 0x0 0x0 0x2 &plic0 58>,
> +					<0x0 0x0 0x0 0x3 &plic0 59>,
> +					<0x0 0x0 0x0 0x4 &plic0 60>;
> +			clock-names = "pcie_aux";
> +			clocks = <&prci PRCI_CLK_PCIE_AUX>;
> +			pwren-gpios = <&gpio 5 0>;
> +			perstn-gpios = <&gpio 8 0>;
> +			resets = <&prci 4>;
> +			status = "okay";
> +		};
>  	};
>  };

Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

I'm happy to take these all through the RISC-V tree if that helps, but 
as usual I'd like reviews or acks from the subsystem maintainers.  It 
looks like there are some issues so I'm going to drop this from my 
inbox.
Greentime Hu April 19, 2021, 2:43 a.m. UTC | #2
Palmer Dabbelt <palmer@dabbelt.com> 於 2021年3月31日 週三 上午8:24寫道:
>
> On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime.hu@sifive.com wrote:
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > index d1bb22b11920..d0839739b425 100644
> > --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -158,6 +158,7 @@ prci: clock-controller@10000000 {
> >                       reg = <0x0 0x10000000 0x0 0x1000>;
> >                       clocks = <&hfclk>, <&rtcclk>;
> >                       #clock-cells = <1>;
> > +                     #reset-cells = <1>;
> >               };
> >               uart0: serial@10010000 {
> >                       compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> > @@ -288,5 +289,38 @@ gpio: gpio@10060000 {
> >                       clocks = <&prci PRCI_CLK_PCLK>;
> >                       status = "disabled";
> >               };
> > +             pcie@e00000000 {
> > +                     #address-cells = <3>;
> > +                     #interrupt-cells = <1>;
> > +                     #num-lanes = <8>;
> > +                     #size-cells = <2>;
> > +                     compatible = "sifive,fu740-pcie";
> > +                     reg = <0xe 0x00000000 0x1 0x0
> > +                            0xd 0xf0000000 0x0 0x10000000
> > +                            0x0 0x100d0000 0x0 0x1000>;
> > +                     reg-names = "dbi", "config", "mgmt";
> > +                     device_type = "pci";
> > +                     dma-coherent;
> > +                     bus-range = <0x0 0xff>;
> > +                     ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
> > +                               0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
> > +                               0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
> > +                               0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
> > +                     num-lanes = <0x8>;
> > +                     interrupts = <56 57 58 59 60 61 62 63 64>;
> > +                     interrupt-names = "msi", "inta", "intb", "intc", "intd";
> > +                     interrupt-parent = <&plic0>;
> > +                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > +                     interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> > +                                     <0x0 0x0 0x0 0x2 &plic0 58>,
> > +                                     <0x0 0x0 0x0 0x3 &plic0 59>,
> > +                                     <0x0 0x0 0x0 0x4 &plic0 60>;
> > +                     clock-names = "pcie_aux";
> > +                     clocks = <&prci PRCI_CLK_PCIE_AUX>;
> > +                     pwren-gpios = <&gpio 5 0>;
> > +                     perstn-gpios = <&gpio 8 0>;
> > +                     resets = <&prci 4>;
> > +                     status = "okay";
> > +             };
> >       };
> >  };
>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> I'm happy to take these all through the RISC-V tree if that helps, but
> as usual I'd like reviews or acks from the subsystem maintainers.  It
> looks like there are some issues so I'm going to drop this from my
> inbox.

Hi Palmer,

Since the subsystem maintainer has pick the first 5 patches to his
branch, would you please help to pick the 6th patch of version 6?
Thank you. :)

https://www.spinics.net/lists/linux-clk/msg57213.html
https://patchwork.kernel.org/project/linux-riscv/patch/20210406092634.50465-7-greentime.hu@sifive.com/
Greentime Hu April 19, 2021, 2:48 a.m. UTC | #3
Greentime Hu <greentime.hu@sifive.com> 於 2021年4月19日 週一 上午10:43寫道:
>
> Palmer Dabbelt <palmer@dabbelt.com> 於 2021年3月31日 週三 上午8:24寫道:
> >
> > On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime.hu@sifive.com wrote:
> > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > > ---
> > >  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > index d1bb22b11920..d0839739b425 100644
> > > --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > @@ -158,6 +158,7 @@ prci: clock-controller@10000000 {
> > >                       reg = <0x0 0x10000000 0x0 0x1000>;
> > >                       clocks = <&hfclk>, <&rtcclk>;
> > >                       #clock-cells = <1>;
> > > +                     #reset-cells = <1>;
> > >               };
> > >               uart0: serial@10010000 {
> > >                       compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> > > @@ -288,5 +289,38 @@ gpio: gpio@10060000 {
> > >                       clocks = <&prci PRCI_CLK_PCLK>;
> > >                       status = "disabled";
> > >               };
> > > +             pcie@e00000000 {
> > > +                     #address-cells = <3>;
> > > +                     #interrupt-cells = <1>;
> > > +                     #num-lanes = <8>;
> > > +                     #size-cells = <2>;
> > > +                     compatible = "sifive,fu740-pcie";
> > > +                     reg = <0xe 0x00000000 0x1 0x0
> > > +                            0xd 0xf0000000 0x0 0x10000000
> > > +                            0x0 0x100d0000 0x0 0x1000>;
> > > +                     reg-names = "dbi", "config", "mgmt";
> > > +                     device_type = "pci";
> > > +                     dma-coherent;
> > > +                     bus-range = <0x0 0xff>;
> > > +                     ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
> > > +                               0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
> > > +                               0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
> > > +                               0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
> > > +                     num-lanes = <0x8>;
> > > +                     interrupts = <56 57 58 59 60 61 62 63 64>;
> > > +                     interrupt-names = "msi", "inta", "intb", "intc", "intd";
> > > +                     interrupt-parent = <&plic0>;
> > > +                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > > +                     interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> > > +                                     <0x0 0x0 0x0 0x2 &plic0 58>,
> > > +                                     <0x0 0x0 0x0 0x3 &plic0 59>,
> > > +                                     <0x0 0x0 0x0 0x4 &plic0 60>;
> > > +                     clock-names = "pcie_aux";
> > > +                     clocks = <&prci PRCI_CLK_PCIE_AUX>;
> > > +                     pwren-gpios = <&gpio 5 0>;
> > > +                     perstn-gpios = <&gpio 8 0>;
> > > +                     resets = <&prci 4>;
> > > +                     status = "okay";
> > > +             };
> > >       };
> > >  };
> >
> > Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >
> > I'm happy to take these all through the RISC-V tree if that helps, but
> > as usual I'd like reviews or acks from the subsystem maintainers.  It
> > looks like there are some issues so I'm going to drop this from my
> > inbox.
>
> Hi Palmer,
>
> Since the subsystem maintainer has pick the first 5 patches to his
> branch, would you please help to pick the 6th patch of version 6?

Sorry there is no version 6, I mean version 5. :p

> Thank you. :)
>
> https://www.spinics.net/lists/linux-clk/msg57213.html
> https://patchwork.kernel.org/project/linux-riscv/patch/20210406092634.50465-7-greentime.hu@sifive.com/

Patch
diff mbox series

diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index d1bb22b11920..d0839739b425 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -158,6 +158,7 @@  prci: clock-controller@10000000 {
 			reg = <0x0 0x10000000 0x0 0x1000>;
 			clocks = <&hfclk>, <&rtcclk>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 		uart0: serial@10010000 {
 			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@@ -288,5 +289,38 @@  gpio: gpio@10060000 {
 			clocks = <&prci PRCI_CLK_PCLK>;
 			status = "disabled";
 		};
+		pcie@e00000000 {
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#num-lanes = <8>;
+			#size-cells = <2>;
+			compatible = "sifive,fu740-pcie";
+			reg = <0xe 0x00000000 0x1 0x0
+			       0xd 0xf0000000 0x0 0x10000000
+			       0x0 0x100d0000 0x0 0x1000>;
+			reg-names = "dbi", "config", "mgmt";
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
+				  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
+				  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
+				  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
+			num-lanes = <0x8>;
+			interrupts = <56 57 58 59 60 61 62 63 64>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-parent = <&plic0>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+					<0x0 0x0 0x0 0x2 &plic0 58>,
+					<0x0 0x0 0x0 0x3 &plic0 59>,
+					<0x0 0x0 0x0 0x4 &plic0 60>;
+			clock-names = "pcie_aux";
+			clocks = <&prci PRCI_CLK_PCIE_AUX>;
+			pwren-gpios = <&gpio 5 0>;
+			perstn-gpios = <&gpio 8 0>;
+			resets = <&prci 4>;
+			status = "okay";
+		};
 	};
 };