[v2,4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
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Message ID 8008af6d86737b74020d7d8f9c3fbc9b500e9993.1615954046.git.greentime.hu@sifive.com
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  • Add SiFive FU740 PCIe host controller driver support
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Greentime Hu March 18, 2021, 6:08 a.m. UTC
Add PCIe host controller DT bindings of SiFive FU740.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 .../bindings/pci/sifive,fu740-pcie.yaml       | 119 ++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml

Comments

Krzysztof Wilczyński March 19, 2021, 3:56 a.m. UTC | #1
Hi,

Thank you for sending the patches over!

A few nitpicks.

> +title: SiFive fu740 PCIe host controller
> +
> +description:
> +  SiFive fu740 PCIe host controller is based on the Synopsys DesignWare
> +  PCI core. It shares common features with the PCIe DesignWare core and
> +  inherits common properties defined in
> +  Documentation/devicetree/bindings/pci/designware-pcie.txt.
[...]

In the above title and description it would be "FU740" to keep this
consistent with everything else.

Also, as this is a YAML file, a multi-line description might be better
expressed as "description: |" or "description: |+", of course it depends
on whether you would like or not to preserve line endings.

[...]
> +  dma-coherent:
> +    description: Indicates that the PCIe IP block can ensure the coherency
> +
> +  bus-range:
> +    description: Range of bus numbers associated with this controller.
[...]
> +  resets:
> +    description: A phandle to the PCIe power up reset line
> +
> +  pwren-gpios:
> +    description: Should specify the GPIO for controlling the PCI bus device power on
> +
> +  perstn-gpios:
> +    description: Should specify the GPIO for controlling the PCI bus device reset
[...]

All the above descriptions should end with a period, so that we keep
things consistent throughout.

Krzysztof
Rob Herring March 19, 2021, 9:49 p.m. UTC | #2
On Thu, 18 Mar 2021 14:08:11 +0800, Greentime Hu wrote:
> Add PCIe host controller DT bindings of SiFive FU740.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  .../bindings/pci/sifive,fu740-pcie.yaml       | 119 ++++++++++++++++++
>  1 file changed, 119 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dts:45.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1380: dt_binding_check] Error 2

See https://patchwork.ozlabs.org/patch/1455121

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Rob Herring March 23, 2021, 8:35 p.m. UTC | #3
On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote:
> Add PCIe host controller DT bindings of SiFive FU740.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  .../bindings/pci/sifive,fu740-pcie.yaml       | 119 ++++++++++++++++++
>  1 file changed, 119 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> new file mode 100644
> index 000000000000..c25a91b18cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive fu740 PCIe host controller
> +
> +description:
> +  SiFive fu740 PCIe host controller is based on the Synopsys DesignWare
> +  PCI core. It shares common features with the PCIe DesignWare core and
> +  inherits common properties defined in
> +  Documentation/devicetree/bindings/pci/designware-pcie.txt.
> +
> +maintainers:
> +  - Paul Walmsley <paul.walmsley@sifive.com>
> +  - Greentime Hu <greentime.hu@sifive.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: sifive,fu740-pcie
> +
> +  reg:
> +    maxItems: 4

What's the 4th item because there's only 3 names:

> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: config
> +      - const: mgmt
> +
> +  device_type:
> +    const: pci

Already in pci-bus.yaml

> +
> +  dma-coherent:
> +    description: Indicates that the PCIe IP block can ensure the coherency
> +
> +  bus-range:
> +    description: Range of bus numbers associated with this controller.

Already in pci-bus.yaml

> +
> +  num-lanes: true

Need to define possible values if not all of 1,2,4,8,16.

> +
> +  msi-parent: true
> +
> +  interrupt-names:
> +    items:
> +      - const: msi
> +      - const: inta
> +      - const: intb
> +      - const: intc
> +      - const: intd
> +
> +  resets:
> +    description: A phandle to the PCIe power up reset line
> +
> +  pwren-gpios:
> +    description: Should specify the GPIO for controlling the PCI bus device power on

maxItems: 1

> +
> +  perstn-gpios:
> +    description: Should specify the GPIO for controlling the PCI bus device reset

The DWC binding and pci.txt already define 'reset-gpios' for this 
purpose.

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - device_type

pci-bus.yaml already requires this.

> +  - dma-coherent
> +  - bus-range

This generally doesn't need to be required unless the h/w can't support 
0-0xff.

> +  - ranges

pci-bus.yaml already requires this.

> +  - num-lanes
> +  - interrupts
> +  - interrupt-names
> +  - interrupt-parent
> +  - interrupt-map-mask
> +  - interrupt-map
> +  - clock-names
> +  - clocks
> +  - resets
> +  - pwren-gpios
> +  - perstn-gpios
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    pcie@e00000000 {
> +        #address-cells = <3>;
> +        #interrupt-cells = <1>;
> +        #size-cells = <2>;
> +        compatible = "sifive,fu740-pcie";
> +        reg = <0xe 0x00000000 0x1 0x0

Humm, 4GB for DBI space? The DWC controller doesn't have that much 
space, and the kernel will map *all* of that. That's not an 
insignificant amount of memory just for page tables.

> +               0xd 0xf0000000 0x0 0x10000000
> +               0x0 0x100d0000 0x0 0x1000>;

<> around each reg entry.

> +        reg-names = "dbi", "config", "mgmt";
> +        device_type = "pci";
> +        dma-coherent;
> +        bus-range = <0x0 0xff>;
> +        ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
> +                  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
> +                  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
> +                  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */

<> around each ranges entry.

> +        num-lanes = <0x8>;
> +        interrupts = <56 57 58 59 60 61 62 63 64>;

And here.

> +        interrupt-names = "msi", "inta", "intb", "intc", "intd";
> +        interrupt-parent = <&plic0>;
> +        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> +        interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> +                        <0x0 0x0 0x0 0x2 &plic0 58>,
> +                        <0x0 0x0 0x0 0x3 &plic0 59>,
> +                        <0x0 0x0 0x0 0x4 &plic0 60>;
> +        clock-names = "pcie_aux";
> +        clocks = <&prci PRCI_CLK_PCIE_AUX>;
> +        resets = <&prci 4>;
> +        pwren-gpios = <&gpio 5 0>;
> +        perstn-gpios = <&gpio 8 0>;
> +    };
> -- 
> 2.30.2
>
Greentime Hu March 29, 2021, 3:39 a.m. UTC | #4
Rob Herring <robh@kernel.org> 於 2021年3月24日 週三 上午4:35寫道:
>
> On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote:
> > Add PCIe host controller DT bindings of SiFive FU740.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  .../bindings/pci/sifive,fu740-pcie.yaml       | 119 ++++++++++++++++++
> >  1 file changed, 119 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
[...]
> > +examples:
> > +  - |
> > +    pcie@e00000000 {
> > +        #address-cells = <3>;
> > +        #interrupt-cells = <1>;
> > +        #size-cells = <2>;
> > +        compatible = "sifive,fu740-pcie";
> > +        reg = <0xe 0x00000000 0x1 0x0
>
> Humm, 4GB for DBI space? The DWC controller doesn't have that much
> space, and the kernel will map *all* of that. That's not an
> insignificant amount of memory just for page tables.

Thank you for review and point this out. :)

I check the spec description for DBI in DWC_pcie_ctl_dm_databook.pdf
section 3.15 3.16 and table 3-17.

I think CX_SRIOV_ENABLE and CX_ARI_ENABLE will be set to 0 because
these 2 are endpoint mode features.
Single Root I/O Virtualization (SR-IOV) This section describes the
SR-IOV features implemented in EP mode. The parameter for enabling
SR-IOV is CX_SRIOV_ENABLE
Alternative Routing-ID Interpretation (ARI) ARI allows an endpoint to
support more than eight physical functions (PFs). ARI is enabled by
the CX_ARI_ENABLE parameter.

So based on Table 3-17, we will need to map 2GB(bit30) instead of 4GB(bit31).

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
new file mode 100644
index 000000000000..c25a91b18cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
@@ -0,0 +1,119 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive fu740 PCIe host controller
+
+description:
+  SiFive fu740 PCIe host controller is based on the Synopsys DesignWare
+  PCI core. It shares common features with the PCIe DesignWare core and
+  inherits common properties defined in
+  Documentation/devicetree/bindings/pci/designware-pcie.txt.
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Greentime Hu <greentime.hu@sifive.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: sifive,fu740-pcie
+
+  reg:
+    maxItems: 4
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+      - const: mgmt
+
+  device_type:
+    const: pci
+
+  dma-coherent:
+    description: Indicates that the PCIe IP block can ensure the coherency
+
+  bus-range:
+    description: Range of bus numbers associated with this controller.
+
+  num-lanes: true
+
+  msi-parent: true
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+  resets:
+    description: A phandle to the PCIe power up reset line
+
+  pwren-gpios:
+    description: Should specify the GPIO for controlling the PCI bus device power on
+
+  perstn-gpios:
+    description: Should specify the GPIO for controlling the PCI bus device reset
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - device_type
+  - dma-coherent
+  - bus-range
+  - ranges
+  - num-lanes
+  - interrupts
+  - interrupt-names
+  - interrupt-parent
+  - interrupt-map-mask
+  - interrupt-map
+  - clock-names
+  - clocks
+  - resets
+  - pwren-gpios
+  - perstn-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie@e00000000 {
+        #address-cells = <3>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        compatible = "sifive,fu740-pcie";
+        reg = <0xe 0x00000000 0x1 0x0
+               0xd 0xf0000000 0x0 0x10000000
+               0x0 0x100d0000 0x0 0x1000>;
+        reg-names = "dbi", "config", "mgmt";
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
+                  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
+                  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
+                  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
+        num-lanes = <0x8>;
+        interrupts = <56 57 58 59 60 61 62 63 64>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-parent = <&plic0>;
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+                        <0x0 0x0 0x0 0x2 &plic0 58>,
+                        <0x0 0x0 0x0 0x3 &plic0 59>,
+                        <0x0 0x0 0x0 0x4 &plic0 60>;
+        clock-names = "pcie_aux";
+        clocks = <&prci PRCI_CLK_PCIE_AUX>;
+        resets = <&prci 4>;
+        pwren-gpios = <&gpio 5 0>;
+        perstn-gpios = <&gpio 8 0>;
+    };