From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/apic] x86/vector: Add a sanity check to prevent IRQ2 allocations
Date: Mon, 29 Mar 2021 22:44:40 -0000 [thread overview]
Message-ID: <161705788092.29796.9852234771468172792.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20210318192819.795280387@linutronix.de>
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 9a98bc2cf08a095367449b3548c3d9ad4ad2cd20
Gitweb: https://git.kernel.org/tip/9a98bc2cf08a095367449b3548c3d9ad4ad2cd20
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Thu, 18 Mar 2021 20:26:48 +01:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 30 Mar 2021 00:39:12 +02:00
x86/vector: Add a sanity check to prevent IRQ2 allocations
To prevent another incidental removal of the IRQ2 ignore logic in the
IO/APIC code going unnoticed add a sanity check. Add some commentry at the
other place which ignores IRQ2 while at it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20210318192819.795280387@linutronix.de
---
arch/x86/kernel/apic/vector.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
index 3c9c749..9b75a70 100644
--- a/arch/x86/kernel/apic/vector.c
+++ b/arch/x86/kernel/apic/vector.c
@@ -543,6 +543,14 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
return -ENOSYS;
+ /*
+ * Catch any attempt to touch the cascade interrupt on a PIC
+ * equipped system.
+ */
+ if (WARN_ON_ONCE(info->flags & X86_IRQ_ALLOC_LEGACY &&
+ virq == PIC_CASCADE_IR))
+ return -EINVAL;
+
for (i = 0; i < nr_irqs; i++) {
irqd = irq_domain_get_irq_data(domain, virq + i);
BUG_ON(!irqd);
@@ -745,6 +753,11 @@ void __init lapic_assign_system_vectors(void)
/* Mark the preallocated legacy interrupts */
for (i = 0; i < nr_legacy_irqs(); i++) {
+ /*
+ * Don't touch the cascade interrupt. It's unusable
+ * on PIC equipped machines. See the large comment
+ * in the IO/APIC code.
+ */
if (i != PIC_CASCADE_IR)
irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
}
prev parent reply other threads:[~2021-03-29 22:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-18 19:26 [patch 0/2] x86/ioapic: Restore the ignore IRQ2 routing entry logic Thomas Gleixner
2021-03-18 19:26 ` [patch 1/2] x86/ioapic: Ignore IRQ2 again Thomas Gleixner
2021-03-19 11:50 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner
2021-03-18 19:26 ` [patch 2/2] x86/vector: Add a sanity check to prevent IRQ2 allocations Thomas Gleixner
2021-03-29 22:44 ` tip-bot2 for Thomas Gleixner [this message]
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