From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: ezequiel@collabora.com, p.zabel@pengutronix.de,
mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, lee.jones@linaro.org,
gregkh@linuxfoundation.org, mripard@kernel.org,
paul.kocialkowski@bootlin.com, wens@csie.org,
jernej.skrabec@siol.net, hverkuil-cisco@xs4all.nl,
emil.l.velikov@gmail.com
Cc: kernel@pengutronix.de, linux-imx@nxp.com,
linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org,
kernel@collabora.com,
Benjamin Gaignard <benjamin.gaignard@collabora.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH v8 02/13] dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support
Date: Thu, 1 Apr 2021 17:59:52 +0200 [thread overview]
Message-ID: <20210401160003.88803-3-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210401160003.88803-1-benjamin.gaignard@collabora.com>
Introducing G2 hevc video decoder lead to modify the bindings to allow
to get one node per VPUs.
VPUs share one hardware control block which is provided as a phandle on
an syscon.
Each node got now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
version 7:
- Add Rob and Philipp reviewed-by tag
- Change syscon phandle name to nxp,imx8m-vpu-ctrl (remove 'q' to be
usable for iMX8MM too)
version 5:
- This version doesn't break the backward compatibilty between kernel
and DT.
.../bindings/media/nxp,imx8mq-vpu.yaml | 53 ++++++++++++-------
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
index 762be3f96ce9..18e7d40a5f24 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -15,22 +15,18 @@ description:
properties:
compatible:
- const: nxp,imx8mq-vpu
+ oneOf:
+ - const: nxp,imx8mq-vpu
+ - const: nxp,imx8mq-vpu-g2
reg:
- maxItems: 3
-
- reg-names:
- items:
- - const: g1
- - const: g2
- - const: ctrl
+ maxItems: 1
interrupts:
- maxItems: 2
+ maxItems: 1
interrupt-names:
- items:
+ oneOf:
- const: g1
- const: g2
@@ -46,14 +42,18 @@ properties:
power-domains:
maxItems: 1
+ nxp,imx8m-vpu-ctrl:
+ description: Specifies a phandle to syscon VPU hardware control block
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
required:
- compatible
- reg
- - reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
+ - nxp,imx8m-vpu-ctrl
additionalProperties: false
@@ -62,18 +62,33 @@ examples:
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- vpu: video-codec@38300000 {
+ vpu_ctrl: syscon@38320000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
clock-names = "g1", "g2", "bus";
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
--
2.25.1
next prev parent reply other threads:[~2021-04-01 18:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 15:59 [PATCH v8 00/13] Add HANTRO G2/HEVC decoder support for IMX8MQ Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 01/13] dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to syscon list Benjamin Gaignard
2021-04-06 10:54 ` Hans Verkuil
2021-04-01 15:59 ` Benjamin Gaignard [this message]
2021-04-06 10:57 ` [PATCH v8 02/13] dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support Hans Verkuil
2021-04-01 15:59 ` [PATCH v8 03/13] media: hantro: Use syscon instead of 'ctrl' register Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 04/13] media: hevc: Add fields and flags for hevc PPS Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 05/13] media: hevc: Add decode params control Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 06/13] media: hantro: change hantro_codec_ops run prototype to return errors Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 07/13] media: hantro: Define HEVC codec profiles and supported features Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 08/13] media: hantro: Only use postproc when post processed formats are defined Benjamin Gaignard
2021-04-01 15:59 ` [PATCH v8 09/13] media: uapi: Add a control for HANTRO driver Benjamin Gaignard
2021-04-02 12:27 ` Ezequiel Garcia
2021-04-01 16:00 ` [PATCH v8 10/13] media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control Benjamin Gaignard
2021-04-01 16:00 ` [PATCH v8 11/13] media: hantro: Introduce G2/HEVC decoder Benjamin Gaignard
2021-04-01 16:00 ` [PATCH v8 12/13] media: hantro: IMX8M: add variant for G2/HEVC codec Benjamin Gaignard
2021-04-01 16:00 ` [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware Benjamin Gaignard
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