From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv4 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Tue, 6 Apr 2021 17:04:47 +0800 [thread overview]
Message-ID: <20210406090449.36352-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20210406090449.36352-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V4:
- Rebased against the latest code base
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index d633c1fabdb4..8231f6729385 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.17.1
next prev parent reply other threads:[~2021-04-06 8:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-06 9:04 [PATCHv4 0/6] PCI: layerscape: Add power management support Zhiqiang Hou
2021-04-06 9:04 ` [PATCHv4 1/6] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2021-04-06 9:04 ` [PATCHv4 2/6] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2021-04-06 9:04 ` [PATCHv4 3/6] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2021-04-06 9:04 ` Zhiqiang Hou [this message]
2021-04-06 9:04 ` [PATCHv4 5/6] arm64: dts: ls1043a: Add SCFG phandle " Zhiqiang Hou
2021-04-06 9:04 ` [PATCHv4 6/6] PCI: layerscape: Add power management support Zhiqiang Hou
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