From: Adrien Grassein <adrien.grassein@gmail.com>
To: unlisted-recipients:; (no To-header on input)
Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org,
peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com,
alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org,
andrew.smirnov@gmail.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Adrien Grassein <adrien.grassein@gmail.com>
Subject: [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
Date: Wed, 7 Apr 2021 23:21:20 +0200 [thread overview]
Message-ID: <20210407212122.626137-6-adrien.grassein@gmail.com> (raw)
In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com>
Add description for 3 domains of the i.MX8MM:
- HSIO
- USB OTG 1
- USB OTG 2
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 69 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index d97a53502753..571d0381dd87 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -17,6 +17,8 @@
#include <linux/sizes.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/power/imx8mm-power.h>
+
#define GPC_LPCR_A_CORE_BSC 0x000
@@ -42,6 +44,9 @@
#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
#define IMX8M_MIPI_A53_DOMAIN BIT(2)
+#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
+#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -65,6 +70,9 @@
#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
+#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
+#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
#define GPC_PU_PWRHSK 0x1fc
@@ -76,6 +84,9 @@
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
#define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
+#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
+#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -98,6 +109,9 @@
#define IMX8M_PGC_MIPI_CSI2 28
#define IMX8M_PGC_PCIE2 29
+#define IMX8MM_PGC_OTG1 18
+#define IMX8MM_PGC_OTG2 19
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -572,6 +586,60 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.reg_access_table = &imx8m_access_table,
};
+static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
+ [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
+ .genpd = {
+ .name = "hsiomix",
+ },
+ .bits = {
+ .hsk_req = IMX8MM_HSIO_HSK_PWRDNREQN,
+ .hsk_ack = IMX8MM_HSIO_HSK_PWRDNACKN,
+ },
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
+ .map = IMX8MM_OTG1_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG1,
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
+ .map = IMX8MM_OTG2_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG2,
+ },
+};
+
+static const struct regmap_range imx8mm_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ GPC_PU_PWRHSK),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
+ GPC_PGC_SR(IMX8MM_PGC_OTG1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
+ GPC_PGC_SR(IMX8MM_PGC_OTG2)),
+};
+
+static const struct regmap_access_table imx8mm_access_table = {
+ .yes_ranges = imx8mm_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
+ .domains = imx8mm_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
+ .reg_access_table = &imx8mm_access_table,
+};
+
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
{
int i, ret;
@@ -766,6 +834,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
+ { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ }
};
--
2.25.1
next prev parent reply other threads:[~2021-04-07 21:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 21:21 [PATCH v1 0/7] imx-gpcv2 improvements Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers Adrien Grassein
2021-04-12 17:16 ` Andrey Smirnov
2021-04-07 21:21 ` [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 4/7] dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein [this message]
2021-04-07 21:21 ` [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains Adrien Grassein
2021-04-07 22:13 ` [PATCH v1 0/7] imx-gpcv2 improvements Lucas Stach
2021-04-07 23:03 ` Adam Ford
2021-04-08 1:27 ` Peng Fan (OSS)
2021-04-09 13:36 ` Adam Ford
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