linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
	<kvmarm@lists.cs.columbia.edu>, <linux-kernel@vger.kernel.org>
Cc: <maz@kernel.org>, <will@kernel.org>, <catalin.marinas@arm.com>,
	<james.morse@arm.com>, <julien.thierry.kdev@gmail.com>,
	<suzuki.poulose@arm.com>, <jean-philippe@linaro.org>,
	<julien@xen.org>, <linuxarm@huawei.com>
Subject: [PATCH v4 06/16] arm64/mm: Introduce NUM_CTXT_ASIDS
Date: Wed, 14 Apr 2021 12:23:02 +0100	[thread overview]
Message-ID: <20210414112312.13704-7-shameerali.kolothum.thodi@huawei.com> (raw)
In-Reply-To: <20210414112312.13704-1-shameerali.kolothum.thodi@huawei.com>

From: Julien Grall <julien.grall@arm.com>

At the moment ASID_FIRST_VERSION is used to know the number of ASIDs
supported. As we are going to move the ASID allocator to a separate file,
it would be better to use a different name for external users.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
---
v3-->v4
 -Dropped patch #6, but retained the name NUM_CTXT_ASIDS.

---
 arch/arm64/mm/context.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 628304e0d3b1..0f11d7c7f6a3 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -41,9 +41,9 @@ static unsigned long nr_pinned_asids;
 static unsigned long *pinned_asid_map;
 
 #define ASID_MASK(info)			(~GENMASK((info)->bits - 1, 0))
-#define ASID_FIRST_VERSION(info)	(1UL << (info)->bits)
+#define NUM_CTXT_ASIDS(info)		(1UL << ((info)->bits))
+#define ASID_FIRST_VERSION(info)        NUM_CTXT_ASIDS(info)
 
-#define NUM_USER_ASIDS(info)		ASID_FIRST_VERSION(info)
 #define asid2idx(info, asid)		((asid) & ~ASID_MASK(info))
 #define idx2asid(info, idx)		asid2idx(info, idx)
 
@@ -87,7 +87,7 @@ void verify_cpu_asid_bits(void)
 
 static void set_kpti_asid_bits(struct asid_info *info, unsigned long *map)
 {
-	unsigned int len = BITS_TO_LONGS(NUM_USER_ASIDS(info)) * sizeof(unsigned long);
+	unsigned int len = BITS_TO_LONGS(NUM_CTXT_ASIDS(info)) * sizeof(unsigned long);
 	/*
 	 * In case of KPTI kernel/user ASIDs are allocated in
 	 * pairs, the bottom bit distinguishes the two: if it
@@ -100,11 +100,11 @@ static void set_kpti_asid_bits(struct asid_info *info, unsigned long *map)
 static void set_reserved_asid_bits(struct asid_info *info)
 {
 	if (pinned_asid_map)
-		bitmap_copy(info->map, pinned_asid_map, NUM_USER_ASIDS(info));
+		bitmap_copy(info->map, pinned_asid_map, NUM_CTXT_ASIDS(info));
 	else if (arm64_kernel_unmapped_at_el0())
 		set_kpti_asid_bits(info, info->map);
 	else
-		bitmap_clear(info->map, 0, NUM_USER_ASIDS(info));
+		bitmap_clear(info->map, 0, NUM_CTXT_ASIDS(info));
 }
 
 #define asid_gen_match(asid, info) \
@@ -204,8 +204,8 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid,
 	 * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd
 	 * pairs.
 	 */
-	asid = find_next_zero_bit(info->map, NUM_USER_ASIDS(info), info->map_idx);
-	if (asid != NUM_USER_ASIDS(info))
+	asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), info->map_idx);
+	if (asid != NUM_CTXT_ASIDS(info))
 		goto set_asid;
 
 	/* We're out of ASIDs, so increment the global generation count */
@@ -214,7 +214,7 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid,
 	flush_context(info);
 
 	/* We have more ASIDs than CPUs, so this will always succeed */
-	asid = find_next_zero_bit(info->map, NUM_USER_ASIDS(info), 1);
+	asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), 1);
 
 set_asid:
 	__set_bit(asid, info->map);
@@ -387,7 +387,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
 static int asids_update_limit(void)
 {
 	struct asid_info *info = &asid_info;
-	unsigned long num_available_asids = NUM_USER_ASIDS(info);
+	unsigned long num_available_asids = NUM_CTXT_ASIDS(info);
 
 	if (arm64_kernel_unmapped_at_el0()) {
 		num_available_asids /= 2;
@@ -418,18 +418,18 @@ static int asids_init(void)
 
 	info->bits = get_cpu_asid_bits();
 	atomic64_set(&info->generation, ASID_FIRST_VERSION(info));
-	info->map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS(info)),
+	info->map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)),
 			    sizeof(*info->map), GFP_KERNEL);
 	if (!info->map)
 		panic("Failed to allocate bitmap for %lu ASIDs\n",
-		      NUM_USER_ASIDS(info));
+		      NUM_CTXT_ASIDS(info));
 
 	info->map_idx = 1;
 	info->active = &active_asids;
 	info->reserved = &reserved_asids;
 	raw_spin_lock_init(&info->lock);
 
-	pinned_asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS(info)),
+	pinned_asid_map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)),
 				  sizeof(*pinned_asid_map), GFP_KERNEL);
 	nr_pinned_asids = 0;
 
-- 
2.17.1


  parent reply	other threads:[~2021-04-14 11:25 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14 11:22 [PATCH v4 00/16] kvm/arm: Align the VMID allocation with the arm64 ASID one Shameer Kolothum
2021-04-14 11:22 ` [PATCH v4 01/16] arm64/mm: Introduce asid_info structure and move asid_generation/asid_map to it Shameer Kolothum
2021-04-14 11:22 ` [PATCH v4 02/16] arm64/mm: Move active_asids and reserved_asids to asid_info Shameer Kolothum
2021-04-14 11:22 ` [PATCH v4 03/16] arm64/mm: Move bits " Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 04/16] arm64/mm: Move the variable lock and tlb_flush_pending " Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 05/16] arm64/mm: Remove dependency on MM in new_context Shameer Kolothum
2021-04-14 11:23 ` Shameer Kolothum [this message]
2021-04-14 11:23 ` [PATCH v4 07/16] arm64/mm: Move Pinned ASID related variables to asid_info Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 08/16] arm64/mm: Split asid_inits in 2 parts Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 09/16] arm64/mm: Split the function check_and_switch_context in 3 parts Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 10/16] arm64/mm: Split the arm64_mm_context_get/put Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 11/16] arm64/mm: Introduce a callback to flush the local context Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 12/16] arm64/mm: Introduce a callback to set reserved bits Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 13/16] arm64: Move the ASID allocator code in a separate file Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 14/16] arm64/lib: Add an helper to free memory allocated by the ASID allocator Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 15/16] arch/arm64: Introduce a capability to tell whether 16-bit VMID is available Shameer Kolothum
2021-04-14 11:23 ` [PATCH v4 16/16] kvm/arm: Align the VMID allocation with the arm64 ASID one Shameer Kolothum
2021-04-22 16:08 ` [PATCH v4 00/16] " Will Deacon
2021-04-23  8:31   ` Shameerali Kolothum Thodi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210414112312.13704-7-shameerali.kolothum.thodi@huawei.com \
    --to=shameerali.kolothum.thodi@huawei.com \
    --cc=catalin.marinas@arm.com \
    --cc=james.morse@arm.com \
    --cc=jean-philippe@linaro.org \
    --cc=julien.thierry.kdev@gmail.com \
    --cc=julien@xen.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linuxarm@huawei.com \
    --cc=maz@kernel.org \
    --cc=suzuki.poulose@arm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).