From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
<stefanc@marvell.com>, <oferh@marvell.com>,
Ben Peled <bpeled@marvell.com>
Subject: [”PATCH” v2 2/5] PCI: armada8k: Add link-down handle
Date: Wed, 14 Apr 2021 16:20:51 +0300 [thread overview]
Message-ID: <1618406454-7953-3-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com>
From: Ben Peled <bpeled@marvell.com>
In PCIE ISR routine caused by RST_LINK_DOWN
we schedule work to handle the link-down procedure.
Link-down procedure will:
1. Remove PCIe bus
2. Reset the MAC
3. Reconfigure link back up
4. Rescan PCIe bus
Signed-off-by: Ben Peled <bpeled@marvell.com>
---
drivers/pci/controller/dwc/pcie-armada8k.c | 69 ++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b2278b1..34b253c 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -22,6 +22,8 @@
#include <linux/resource.h>
#include <linux/of_pci.h>
#include <linux/of_irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#include "pcie-designware.h"
@@ -33,6 +35,9 @@ struct armada8k_pcie {
struct clk *clk_reg;
struct phy *phy[ARMADA8K_PCIE_MAX_LANES];
unsigned int phy_count;
+ struct regmap *sysctrl_base;
+ u32 mac_rest_bitmask;
+ struct work_struct recover_link_work;
};
#define PCIE_VENDOR_REGS_OFFSET 0x8000
@@ -73,6 +78,8 @@ struct armada8k_pcie {
#define AX_USER_DOMAIN_MASK 0x3
#define AX_USER_DOMAIN_SHIFT 4
+#define UNIT_SOFT_RESET_CONFIG_REG 0x268
+
#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie)
@@ -225,6 +232,50 @@ static int armada8k_pcie_host_init(struct pcie_port *pp)
return 0;
}
+static void armada8k_pcie_recover_link(struct work_struct *ws)
+{
+ struct armada8k_pcie *pcie = container_of(ws, struct armada8k_pcie, recover_link_work);
+ struct pcie_port *pp = &pcie->pci->pp;
+ struct pci_bus *bus = pp->bridge->bus;
+ struct pci_dev *root_port;
+ int ret;
+
+ root_port = pci_get_slot(bus, 0);
+ if (!root_port) {
+ dev_err(pcie->pci->dev, "failed to get root port\n");
+ return;
+ }
+ pci_lock_rescan_remove();
+ pci_stop_and_remove_bus_device(root_port);
+ /*
+ * Sleep needed to make sure all pcie transactions and access
+ * are flushed before resetting the mac
+ */
+ msleep(100);
+
+ /* Reset mac */
+ regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG,
+ pcie->mac_rest_bitmask, 0, NULL, false, true);
+ udelay(1);
+ regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG,
+ pcie->mac_rest_bitmask, pcie->mac_rest_bitmask,
+ NULL, false, true);
+ udelay(1);
+ ret = armada8k_pcie_host_init(pp);
+ if (ret) {
+ dev_err(pcie->pci->dev, "failed to initialize host: %d\n", ret);
+ pci_unlock_rescan_remove();
+ pci_dev_put(root_port);
+ return;
+ }
+
+ bus = NULL;
+ while ((bus = pci_find_next_bus(bus)) != NULL)
+ pci_rescan_bus(bus);
+ pci_unlock_rescan_remove();
+ pci_dev_put(root_port);
+}
+
static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
{
struct armada8k_pcie *pcie = arg;
@@ -262,6 +313,9 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
* initiate a link retrain. If link retrains were
* possible, that is.
*/
+ if (pcie->sysctrl_base && pcie->mac_rest_bitmask)
+ schedule_work(&pcie->recover_link_work);
+
dev_dbg(pci->dev, "%s: link went down\n", __func__);
}
@@ -330,6 +384,8 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
pcie->pci = pci;
+ INIT_WORK(&pcie->recover_link_work, armada8k_pcie_recover_link);
+
pcie->clk = devm_clk_get(dev, NULL);
if (IS_ERR(pcie->clk))
return PTR_ERR(pcie->clk);
@@ -357,6 +413,19 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
goto fail_clkreg;
}
+ pcie->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "marvell,system-controller");
+ if (IS_ERR(pcie->sysctrl_base)) {
+ dev_warn(dev, "failed to find marvell,system-controller\n");
+ pcie->sysctrl_base = 0x0;
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "marvell,mac-reset-bit-mask",
+ &pcie->mac_rest_bitmask);
+ if (ret < 0) {
+ dev_warn(dev, "couldn't find mac reset bit mask: %d\n", ret);
+ pcie->mac_rest_bitmask = 0x0;
+ }
ret = armada8k_pcie_setup_phys(pcie);
if (ret)
goto fail_clkreg;
--
2.7.4
next prev parent reply other threads:[~2021-04-14 13:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 13:20 [”PATCH” v2 0/5] Asynchronous linkdown recovery bpeled
2021-04-14 13:20 ` [”PATCH” v2 1/5] PCI: armada8k: Disable LTSSM on link down interrupts bpeled
2021-12-09 11:28 ` Pali Rohár
2021-04-14 13:20 ` bpeled [this message]
2021-04-17 10:51 ` [”PATCH” v2 2/5] PCI: armada8k: Add link-down handle Pali Rohár
2021-04-14 13:20 ` [”PATCH” v2 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings bpeled
2021-04-15 21:20 ` Rob Herring
2021-04-14 13:20 ` [”PATCH” v2 4/5] arm64: dts: marvell: add pcie mac reset to pcie bpeled
2021-04-14 13:20 ` [”PATCH” v2 5/5] PCI: armada8k: add device reset to link-down handle bpeled
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