[5.10,19/25] riscv,entry: fix misaligned base for excp_vect_table
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Message ID 20210415144413.761162858@linuxfoundation.org
State New
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  • Untitled series #495371
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Commit Message

Greg Kroah-Hartman April 15, 2021, 2:48 p.m. UTC
From: Zihao Yu <yuzihao@ict.ac.cn>

[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
 arch/riscv/kernel/entry.S | 1 +
 1 file changed, 1 insertion(+)

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diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 744f3209c48d..76274a4a1d8e 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -447,6 +447,7 @@  ENDPROC(__switch_to)
 	.section ".rodata"
+	.align LGREG
 	/* Exception vector table */
 	RISCV_PTR do_trap_insn_misaligned