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From: Qii Wang <qii.wang@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <linux-i2c@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
	<qii.wang@mediatek.com>
Subject: [PATCH 2/3] i2c: mediatek: Fix wrong dma sync flag
Date: Sat, 17 Apr 2021 14:46:51 +0800	[thread overview]
Message-ID: <1618642012-10444-3-git-send-email-qii.wang@mediatek.com> (raw)
In-Reply-To: <1618642012-10444-1-git-send-email-qii.wang@mediatek.com>

The right flag is apdma_sync when apdma remove hand-shake signel.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
 drivers/i2c/busses/i2c-mt65xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 3e34261..bf25acb 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -479,7 +479,7 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 {
 	u16 control_reg;
 
-	if (i2c->dev_comp->dma_sync) {
+	if (i2c->dev_comp->apdma_sync) {
 		writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
 		udelay(10);
 		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
-- 
1.9.1


  parent reply	other threads:[~2021-04-17  6:47 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-17  6:46 [PATCH 0/3] Add some fix patches Qii Wang
2021-04-17  6:46 ` [PATCH 1/3] i2c: mediatek: Fix send master code at more than 1MHz Qii Wang
2021-04-17 20:06   ` Wolfram Sang
2021-04-17  6:46 ` Qii Wang [this message]
2021-04-17 20:07   ` [PATCH 2/3] i2c: mediatek: Fix wrong dma sync flag Wolfram Sang
2021-04-17  6:46 ` [PATCH 3/3] i2c: mediatek: Use scl_int_delay_ns to compensate clock-stretching Qii Wang
2021-04-17 20:09   ` Wolfram Sang

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