[tip:,perf/core] perf/x86/msr: Add Alder Lake CPU support
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Message ID 161891560119.29796.11364634587535953691.tip-bot2@tip-bot2
State Accepted
Commit 19d3a81fd92dc9b73950564955164ecfd0dfbea1
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  • [tip:,perf/core] perf/x86/msr: Add Alder Lake CPU support
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Commit Message

tip-bot2 for Pawan Gupta April 20, 2021, 10:46 a.m. UTC
The following commit has been merged into the perf/core branch of tip:

Commit-ID:     19d3a81fd92dc9b73950564955164ecfd0dfbea1
Gitweb:        https://git.kernel.org/tip/19d3a81fd92dc9b73950564955164ecfd0dfbea1
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Mon, 12 Apr 2021 07:31:03 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Mon, 19 Apr 2021 20:03:29 +02:00

perf/x86/msr: Add Alder Lake CPU support

PPERF and SMI_COUNT MSRs are also supported on Alder Lake.

The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.

The patch has been tested on real hardware.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-24-git-send-email-kan.liang@linux.intel.com
---
 arch/x86/events/msr.c | 2 ++
 1 file changed, 2 insertions(+)

Patch
diff mbox series

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 680404c..c853b28 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -100,6 +100,8 @@  static bool test_intel(int idx, void *data)
 	case INTEL_FAM6_TIGERLAKE_L:
 	case INTEL_FAM6_TIGERLAKE:
 	case INTEL_FAM6_ROCKETLAKE:
+	case INTEL_FAM6_ALDERLAKE:
+	case INTEL_FAM6_ALDERLAKE_L:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;