perf/x86/kvm: Fix Broadwell Xeon stepping in isolation_ucodes[]
diff mbox series

Message ID 20210422001834.1748319-1-jmattson@google.com
State Accepted
Commit 4b2f1e59229b9da319d358828cdfa4ddbc140769
Headers show
Series
  • perf/x86/kvm: Fix Broadwell Xeon stepping in isolation_ucodes[]
Related show

Commit Message

Jim Mattson April 22, 2021, 12:18 a.m. UTC
The only stepping of Broadwell Xeon parts is stepping 1. Fix the
relevant isolation_ucodes[] entry, which previously enumerated
stepping 2.

Although the original commit was characterized as an optimization, it
is also a workaround for a correctness issue.

If a PMI arrives between kvm's call to perf_guest_get_msrs() and the
subsequent VM-entry, a stale value for the IA32_PEBS_ENABLE MSR may be
restored at the next VM-exit. This is because, unbeknownst to kvm, PMI
throttling may clear bits in the IA32_PEBS_ENABLE MSR. CPUs with "PEBS
isolation" don't suffer from this issue, because perf_guest_get_msrs()
doesn't report the IA32_PEBS_ENABLE value.

Fixes: 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary work in guest filtering")
Cc: Andi Kleen <ak@linux.intel.com>
Reported-by: Peter Shier <pshier@google.com>
Signed-off-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Peter Shier <pshier@google.com>
---
 arch/x86/events/intel/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andi Kleen April 22, 2021, 2:05 a.m. UTC | #1
On Wed, Apr 21, 2021 at 05:18:34PM -0700, Jim Mattson wrote:
> The only stepping of Broadwell Xeon parts is stepping 1. Fix the
> relevant isolation_ucodes[] entry, which previously enumerated
> stepping 2.
> 
> Although the original commit was characterized as an optimization, it
> is also a workaround for a correctness issue.
> 
> If a PMI arrives between kvm's call to perf_guest_get_msrs() and the
> subsequent VM-entry, a stale value for the IA32_PEBS_ENABLE MSR may be
> restored at the next VM-exit. This is because, unbeknownst to kvm, PMI
> throttling may clear bits in the IA32_PEBS_ENABLE MSR. CPUs with "PEBS
> isolation" don't suffer from this issue, because perf_guest_get_msrs()
> doesn't report the IA32_PEBS_ENABLE value.

Acked-by: Andi Kleen <ak@linux.intel.com>

-Andi

Patch
diff mbox series

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 37ce38403cb8..c57ec8e27907 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4516,7 +4516,7 @@  static const struct x86_cpu_desc isolation_ucodes[] = {
 	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 3, 0x07000009),
 	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 4, 0x0f000009),
 	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 5, 0x0e000002),
-	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,		 2, 0x0b000014),
+	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,		 1, 0x0b000014),
 	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 3, 0x00000021),
 	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 4, 0x00000000),
 	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 5, 0x00000000),