[09/14] drivers: net: dsa: qca8k: add support for switch rev
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Message ID 20210423014741.11858-10-ansuelsmth@gmail.com
State New, archived
Headers show
Series
  • Multiple improvement to qca8k stability
Related show

Commit Message

Ansuel Smith April 23, 2021, 1:47 a.m. UTC
qca8k switch require some special debug value to be set based on the
switch revision. Rework the switch id read function to also read the
chip revision and make it accessible to the switch data.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 17 ++++++++++++-----
 drivers/net/dsa/qca8k.h |  7 +++++--
 2 files changed, 17 insertions(+), 7 deletions(-)

Patch
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diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index d469620e9344..20b507a35191 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1459,12 +1459,22 @@  static const struct dsa_switch_ops qca8k_switch_ops = {
 	.phylink_mac_link_up	= qca8k_phylink_mac_link_up,
 };
 
+static u8 qca8k_read_switch_id(struct qca8k_priv *priv)
+{
+	u32 val;
+
+	val = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
+
+	priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
+
+	return QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
+}
+
 static int
 qca8k_sw_probe(struct mdio_device *mdiodev)
 {
 	const struct qca8k_match_data *data;
 	struct qca8k_priv *priv;
-	u32 id;
 
 	/* allocate the private data struct so that we can probe the switches
 	 * ID register
@@ -1496,10 +1506,7 @@  qca8k_sw_probe(struct mdio_device *mdiodev)
 		return -ENODEV;
 
 	/* read the switches ID register */
-	id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
-	id >>= QCA8K_MASK_CTRL_ID_S;
-	id &= QCA8K_MASK_CTRL_ID_M;
-	if (id != data->id)
+	if (qca8k_read_switch_id(priv) != data->id)
 		return -ENODEV;
 
 	priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 308d8410fdb6..dbd54d870a30 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -28,8 +28,10 @@ 
 
 /* Global control registers */
 #define QCA8K_REG_MASK_CTRL				0x000
-#define   QCA8K_MASK_CTRL_ID_M				0xff
-#define   QCA8K_MASK_CTRL_ID_S				8
+#define   QCA8K_MASK_CTRL_REV_ID_MASK			GENMASK(7, 0)
+#define   QCA8K_MASK_CTRL_REV_ID(x)			((x) >> 0)
+#define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
+#define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
 #define QCA8K_REG_PORT0_PAD_CTRL			0x004
 #define QCA8K_REG_PORT5_PAD_CTRL			0x008
 #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
@@ -247,6 +249,7 @@  struct qca8k_match_data {
 };
 
 struct qca8k_priv {
+	u8 switch_revision;
 	struct regmap *regmap;
 	struct mii_bus *bus;
 	struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];