From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: vkoul@kernel.org
Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
neil@brown.name, ilya.lipnitskiy@gmail.com
Subject: [PATCH 1/5] staging: mt7621-dts: use clock in pci phy nodes
Date: Thu, 6 May 2021 13:15:27 +0200 [thread overview]
Message-ID: <20210506111531.21978-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com>
MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
Hence we can use the clock in pcie phy nodes to
be able to get it from there in driver code.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 5623d542bcf2..001ff8f51033 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -549,12 +549,16 @@ pcie@2,0 {
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
+ clock-names = "sys_clk";
#phy-cells = <1>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
+ clock-names = "sys_clk";
#phy-cells = <1>;
};
};
--
2.25.1
next prev parent reply other threads:[~2021-05-06 11:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 11:15 [PATCH 0/5] phy: ralink: mt7621-pci-phy: some improvements Sergio Paracuellos
2021-05-06 11:15 ` Sergio Paracuellos [this message]
2021-05-06 11:15 ` [PATCH 2/5] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries Sergio Paracuellos
2021-05-07 22:12 ` Rob Herring
2021-05-08 6:40 ` Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 3/5] phy: ralink: phy-mt7621-pci: use kernel clock APIS Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 4/5] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Sergio Paracuellos
2021-05-06 15:59 ` kernel test robot
2021-05-07 6:13 ` Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 5/5] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Sergio Paracuellos
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