From: Prasad Malisetty <pmaliset@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Rob Herring <robh+dt@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
mgautam@codeaurora.org, swboyd@chromium.org,
dianders@chromium.org, mka@chromium.org,
Prasad Malisetty <pmaliset@codeaurora.org>
Subject: [PATCH] PCIe: qcom: Add support to control pipe clk mux
Date: Sun, 9 May 2021 06:11:00 +0530 [thread overview]
Message-ID: <1620520860-8589-1-git-send-email-pmaliset@codeaurora.org> (raw)
PCIe driver needs to toggle between bi_tcxo and phy pipe
clock as part of its LPM sequence. This is done by setting
pipe_clk/ref_clk_src as parent of pipe_clk_src after phy init
Dependent on below change:
https://lore.kernel.org/patchwork/patch/1422499/
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..a9f69e8 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -9,6 +9,7 @@
*/
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
@@ -166,6 +167,9 @@ struct qcom_pcie_resources_2_7_0 {
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
struct clk *pipe_clk;
+ struct clk *pipe_clk_src;
+ struct clk *pipe_ext_src;
+ struct clk *ref_clk_src;
};
union qcom_pcie_resources {
@@ -1168,7 +1172,19 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
return ret;
res->pipe_clk = devm_clk_get(dev, "pipe");
- return PTR_ERR_OR_ZERO(res->pipe_clk);
+ if (IS_ERR(res->pipe_clk))
+ return PTR_ERR(res->pipe_clk);
+
+ res->pipe_clk_src = devm_clk_get(dev, "pipe_src");
+ if (IS_ERR(res->pipe_clk_src))
+ return PTR_ERR(res->pipe_clk_src);
+
+ res->pipe_ext_src = devm_clk_get(dev, "pipe_ext");
+ if (IS_ERR(res->pipe_ext_src))
+ return PTR_ERR(res->pipe_ext_src);
+
+ res->ref_clk_src = devm_clk_get(dev, "ref");
+ return PTR_ERR_OR_ZERO(res->ref_clk_src);
}
static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
@@ -1255,6 +1271,11 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280"))
+ clk_set_parent(res->pipe_clk_src, res->pipe_ext_src);
return clk_prepare_enable(res->pipe_clk);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next reply other threads:[~2021-05-09 0:41 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-09 0:41 Prasad Malisetty [this message]
2021-05-09 2:35 ` [PATCH] PCIe: qcom: Add support to control pipe clk mux Bjorn Andersson
2021-05-20 10:15 ` Prasad Malisetty
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