From: "tip-bot2 for H. Peter Anvin (Intel)" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "H. Peter Anvin (Intel)" <hpa@zytor.com>,
Ingo Molnar <mingo@kernel.org>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/asm] x86/entry: Split PUSH_AND_CLEAR_REGS into two submacros
Date: Wed, 12 May 2021 09:23:32 -0000 [thread overview]
Message-ID: <162081141225.29796.14095021239413369152.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20210510185316.3307264-6-hpa@zytor.com>
The following commit has been merged into the x86/asm branch of tip:
Commit-ID: 29e9758966f47004bd7245e6adadcb708386f36a
Gitweb: https://git.kernel.org/tip/29e9758966f47004bd7245e6adadcb708386f36a
Author: H. Peter Anvin (Intel) <hpa@zytor.com>
AuthorDate: Mon, 10 May 2021 11:53:14 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 12 May 2021 10:49:15 +02:00
x86/entry: Split PUSH_AND_CLEAR_REGS into two submacros
PUSH_AND_CLEAR_REGS, as the name implies, performs two functions:
pushing registers and clearing registers. They don't necessarily have
to be performed in immediate sequence, although all current users
do. Split it into two macros for the case where that isn't desired;
the FRED enabling patchset will eventually make use of this.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210510185316.3307264-6-hpa@zytor.com
---
arch/x86/entry/calling.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
index 7436d4a..a4c061f 100644
--- a/arch/x86/entry/calling.h
+++ b/arch/x86/entry/calling.h
@@ -63,7 +63,7 @@ For 32-bit we have the following conventions - kernel is built with
* for assembly code:
*/
-.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
+.macro PUSH_REGS rdx=%rdx rax=%rax save_ret=0
.if \save_ret
pushq %rsi /* pt_regs->si */
movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
@@ -90,7 +90,9 @@ For 32-bit we have the following conventions - kernel is built with
.if \save_ret
pushq %rsi /* return address on top of stack */
.endif
+.endm
+.macro CLEAR_REGS
/*
* Sanitize registers of values that a speculation attack might
* otherwise want to exploit. The lower registers are likely clobbered
@@ -112,6 +114,11 @@ For 32-bit we have the following conventions - kernel is built with
.endm
+.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
+ PUSH_REGS rdx=\rdx, rax=\rax, save_ret=\save_ret
+ CLEAR_REGS
+.endm
+
.macro POP_REGS pop_rdi=1 skip_r11rcx=0
popq %r15
popq %r14
next prev parent reply other threads:[~2021-05-12 9:23 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-10 18:53 [RFC v2 PATCH 0/6] x86/entry: cleanups and consistent syscall number handling H. Peter Anvin
2021-05-10 18:53 ` [RFC v2 PATCH 1/7] x86/entry: unify definitions from calling.h and ptrace-abi.h H. Peter Anvin
2021-05-12 9:23 ` [tip: x86/asm] x86/entry: Unify definitions from <asm/calling.h> and <asm/ptrace-abi.h> tip-bot2 for H. Peter Anvin (Intel)
2021-05-10 18:53 ` [RFC v2 PATCH 2/7] x86/entry: reverse arguments to do_syscall_64() H. Peter Anvin
2021-05-12 9:23 ` [tip: x86/asm] x86/entry: Reverse " tip-bot2 for H. Peter Anvin (Intel)
2021-05-10 18:53 ` [RFC v2 PATCH 3/7] x86/syscall: unconditionally prototype {ia32,x32}_sys_call_table[] H. Peter Anvin
2021-05-12 9:23 ` [tip: x86/asm] x86/syscall: Unconditionally " tip-bot2 for H. Peter Anvin (Intel)
2021-05-10 18:53 ` [RFC v2 PATCH 4/7] x86/syscall: maximize MSR_SYSCALL_MASK H. Peter Anvin
2021-05-12 9:23 ` [tip: x86/asm] x86/syscall: Maximize MSR_SYSCALL_MASK tip-bot2 for H. Peter Anvin (Intel)
2021-05-10 18:53 ` [RFC v2 PATCH 5/7] x86/entry: split PUSH_AND_CLEAR_REGS into two submacros H. Peter Anvin
2021-05-12 9:23 ` tip-bot2 for H. Peter Anvin (Intel) [this message]
2021-05-10 18:53 ` [RFC v2 PATCH 6/7] x86/regs: syscall_get_nr() returns -1 for a non-system call H. Peter Anvin
2021-05-12 9:23 ` [tip: x86/asm] x86/regs: Syscall_get_nr() " tip-bot2 for H. Peter Anvin
2021-05-10 18:53 ` [RFC v2 PATCH 7/7] x86/entry: use int for syscall number; handle all invalid syscall nrs H. Peter Anvin
2021-05-12 8:51 ` Ingo Molnar
2021-05-12 17:50 ` H. Peter Anvin
2021-05-12 12:09 ` Thomas Gleixner
2021-05-12 18:21 ` H. Peter Anvin
2021-05-12 18:34 ` Thomas Gleixner
2021-05-12 22:09 ` H. Peter Anvin
2021-05-12 22:22 ` Thomas Gleixner
2021-05-12 22:24 ` H. Peter Anvin
2021-05-14 0:38 ` H. Peter Anvin
2021-05-14 3:18 ` Andy Lutomirski
2021-05-14 3:23 ` H. Peter Anvin
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