From: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
To: Rob Herring <robh+dt@kernel.org>, Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Russell King <linux@armlinux.org.uk>,
David Sterba <dsterba@suse.com>, Jens Axboe <axboe@kernel.dk>,
Bartosz Dudziak <bartosz.dudziak@snejp.pl>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Kumar Gala <galak@codeaurora.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm: qcom: Add SMP support for Cortex-A7
Date: Thu, 13 May 2021 17:34:42 +0200 [thread overview]
Message-ID: <20210513153442.52941-3-bartosz.dudziak@snejp.pl> (raw)
In-Reply-To: <20210513153442.52941-1-bartosz.dudziak@snejp.pl>
Implement support for Cortex-A7 CPU release sequence.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
arch/arm/mach-qcom/platsmp.c | 72 ++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 630a038f45..10780bf14a 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -29,6 +29,7 @@
#define COREPOR_RST BIT(5)
#define CORE_RST BIT(4)
#define L2DT_SLP BIT(3)
+#define CORE_MEM_CLAMP BIT(1)
#define CLAMP BIT(0)
#define APC_PWR_GATE_CTL 0x14
@@ -75,6 +76,63 @@ static int scss_release_secondary(unsigned int cpu)
return 0;
}
+static int cortex_a7_release_secondary(unsigned int cpu)
+{
+ int ret = 0;
+ void __iomem *reg;
+ struct device_node *cpu_node, *acc_node;
+ u32 reg_val;
+
+ cpu_node = of_get_cpu_node(cpu, NULL);
+ if (!cpu_node)
+ return -ENODEV;
+
+ acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+ if (!acc_node) {
+ ret = -ENODEV;
+ goto out_acc;
+ }
+
+ reg = of_iomap(acc_node, 0);
+ if (!reg) {
+ ret = -ENOMEM;
+ goto out_acc_map;
+ }
+
+ /* Put the CPU into reset. */
+ reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+ /* Turn on the BHS, set the BHS_CNT to 16 XO clock cycles */
+ writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
+ /* Wait for the BHS to settle */
+ udelay(2);
+
+ reg_val &= ~CORE_MEM_CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+ reg_val |= L2DT_SLP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ udelay(2);
+
+ reg_val = (reg_val | BIT(17)) & ~CLAMP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ udelay(2);
+
+ /* Release CPU out of reset and bring it to life. */
+ reg_val &= ~(CORE_RST | COREPOR_RST);
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+ reg_val |= CORE_PWRD_UP;
+ writel(reg_val, reg + APCS_CPU_PWR_CTL);
+
+out_acc_map:
+ of_node_put(acc_node);
+out_acc:
+ of_node_put(cpu_node);
+
+ return ret;
+}
+
static int kpssv1_release_secondary(unsigned int cpu)
{
int ret = 0;
@@ -281,6 +339,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
return qcom_boot_secondary(cpu, scss_release_secondary);
}
+static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ return qcom_boot_secondary(cpu, cortex_a7_release_secondary);
+}
+
static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
return qcom_boot_secondary(cpu, kpssv1_release_secondary);
@@ -315,6 +378,15 @@ static const struct smp_operations smp_msm8660_ops __initconst = {
};
CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
+static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
+ .smp_prepare_cpus = qcom_smp_prepare_cpus,
+ .smp_boot_secondary = cortex_a7_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_cortex_a7, "qcom,cpss-acc", &qcom_smp_cortex_a7_ops);
+
static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
.smp_prepare_cpus = qcom_smp_prepare_cpus,
.smp_boot_secondary = kpssv1_boot_secondary,
--
2.25.1
next prev parent reply other threads:[~2021-05-13 15:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-13 15:34 [PATCH 0/2] arm: qcom: Add SMP support for Cortex-A7 Bartosz Dudziak
2021-05-13 15:34 ` [PATCH 1/2] dt-bindings: arm: Document qcom,cpss-acc Bartosz Dudziak
2021-05-18 1:13 ` Rob Herring
2021-05-13 15:34 ` Bartosz Dudziak [this message]
2021-05-25 12:20 ` [PATCH 2/2] arm: qcom: Add SMP support for Cortex-A7 Stephan Gerhold
2021-05-25 18:41 ` Bartosz Dudziak
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