From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Peter De Schrijver" <pdeschrijver@nvidia.com>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Michał Mirosław" <mirq-linux@rere.qmqm.pl>
Cc: Rob Herring <robh+dt@kernel.org>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v8 4/9] clk: tegra: Halve SCLK rate on Tegra20
Date: Sun, 16 May 2021 19:30:36 +0300 [thread overview]
Message-ID: <20210516163041.12818-5-digetx@gmail.com> (raw)
In-Reply-To: <20210516163041.12818-1-digetx@gmail.com>
Higher SCLK rates on Tegra20 require high core voltage. The higher
clock rate may have a positive performance effect only for AHB DMA
transfers and AVP CPU, but both aren't used by upstream kernel at all.
Halve SCLK rate on Tegra20 in order to remove the high core voltage
requirement.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra20.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 3efc651b42e3..3664593a5ba4 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
- { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
- { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
- { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
+ { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
+ { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 },
+ { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
--
2.30.2
next prev parent reply other threads:[~2021-05-16 16:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-16 16:30 [PATCH v8 0/9] Couple improvements for Tegra clk driver Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 1/9] clk: tegra30: Use 300MHz for video decoder by default Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 2/9] clk: tegra: Fix refcounting of gate clocks Dmitry Osipenko
2021-07-14 11:48 ` Jon Hunter
2021-07-14 11:59 ` Dmitry Osipenko
2021-07-14 15:13 ` Dmitry Osipenko
2021-07-14 17:58 ` Jon Hunter
2021-05-16 16:30 ` [PATCH v8 3/9] clk: tegra: Ensure that PLLU configuration is applied properly Dmitry Osipenko
2021-05-16 16:30 ` Dmitry Osipenko [this message]
2021-05-16 16:30 ` [PATCH v8 5/9] clk: tegra: Don't allow zero clock rate for PLLs Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 6/9] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 7/9] clk: tegra: Mark external clocks as not having reset control Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 8/9] clk: tegra: Don't deassert reset on enabling clocks Dmitry Osipenko
2021-05-16 16:30 ` [PATCH v8 9/9] dt-bindings: clock: tegra: Convert to schema Dmitry Osipenko
2021-05-17 2:27 ` Rob Herring
2021-05-31 13:20 ` (subset) [PATCH v8 0/9] Couple improvements for Tegra clk driver Thierry Reding
2021-05-31 13:20 ` Thierry Reding
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