From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
<seiya.wang@mediatek.com>, <wenst@google.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Jitao Shi <jitao.shi@mediatek.com>
Subject: [PATCH 22/27] arm64: dts: mt8195: add edp nodes
Date: Wed, 16 Jun 2021 01:32:28 +0800 [thread overview]
Message-ID: <20210615173233.26682-22-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>
From: Jitao Shi <jitao.shi@mediatek.com>
add edp nodes for mt8195
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++-
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 256818c4c0bf..d7d2c2a8f461 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -23,6 +23,8 @@
aliases {
dpi1 = &disp_dpi1;
+ dp-intf0 = &dp_intf0;
+ dp-intf1 = &dp_intf1;
};
clocks {
@@ -1155,6 +1157,29 @@
status = "disabled";
};
+ disp_pwm0: disp_pwm0@1100e000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>,
+ <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ disp_pwm1: disp_pwm1@1100f000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100f000 0 0x1000>;
+ interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>,
+ <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8195-spi",
"mediatek,mt6765-spi";
@@ -2397,6 +2422,30 @@
status = "disabled";
};
+ dp_intf1: dp_intf1@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&topckgen CLK_TOP_DP_SEL>,
+ <&topckgen CLK_TOP_TVDPLL2_D2>,
+ <&topckgen CLK_TOP_TVDPLL2_D4>,
+ <&topckgen CLK_TOP_TVDPLL2_D8>,
+ <&topckgen CLK_TOP_TVDPLL2_D16>,
+ <&topckgen CLK_TOP_TVDPLL2>;
+ clock-names = "hf_fmm_ck",
+ "hf_fdp_ck",
+ "MUX_DP",
+ "TVDPLL_D2",
+ "TVDPLL_D4",
+ "TVDPLL_D8",
+ "TVDPLL_D16",
+ "DPI_CK";
+ status = "disabled";
+ };
+
hdmi0: hdmi@1c300000 {
compatible = "mediatek,mt8195-hdmi";
reg = <0 0x1c300000 0 0x1000>;
@@ -2421,11 +2470,19 @@
edp_tx: edp_tx@1c500000 {
status = "disabled";
- compatible = "mediatek,mt8195-dp_tx";
+ compatible = "mediatek,mt8195-edp_tx";
reg = <0 0x1c500000 0 0x8000>;
power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
};
+
+ dp_tx: dp_tx@1c600000 {
+ compatible = "mediatek,mt8195-dp_tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
};
hdmiddc0: ddc_i2c {
--
2.18.0
next prev parent reply other threads:[~2021-06-15 17:33 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 17:32 arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Tinghan Shen
2021-06-16 8:01 ` Chen-Yu Tsai
2021-06-15 17:32 ` [PATCH 02/27] arm64: dts: mt8195: add pinctrl node Tinghan Shen
2021-06-15 17:32 ` [PATCH 03/27] arm64: dts: mt8195: add pwrap node Tinghan Shen
2021-06-15 17:32 ` [PATCH 05/27] arm64: dts: mt8195: add spmi node Tinghan Shen
2021-06-15 17:32 ` [PATCH 06/27] arm64: dts: mt8195: add clock controllers Tinghan Shen
2021-06-15 17:32 ` [PATCH 07/27] arm64: dts: mt8195: add power domains controller Tinghan Shen
2021-06-15 17:32 ` [PATCH 08/27] arm64: dts: mt8195: add i2c dts Tinghan Shen
2021-06-15 17:32 ` [PATCH 09/27] arm64: dts: mt8195: add spi controller Tinghan Shen
2021-06-15 17:32 ` [PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node Tinghan Shen
2021-06-15 17:32 ` [PATCH 11/27] arm64: dts: mt8195: add PCIe " Tinghan Shen
2021-06-15 17:32 ` [PATCH 12/27] arm64: dts: mt8195: fix mmc driver Tinghan Shen
2021-06-16 1:30 ` Wenbin Mei
2021-06-15 17:32 ` [PATCH 13/27] arm64: dts: mt8195: add hdmi nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 14/27] arm64: dts: mt8195: add usb support Tinghan Shen
2021-06-15 17:32 ` [PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 16/27] arm64: dts: mt8195: add display node Tinghan Shen
2021-06-15 23:14 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 17/27] arm64: dts: mt8195: add merge node Tinghan Shen
2021-06-15 17:32 ` [PATCH 18/27] arm64: dts: mt8195: add dsc node Tinghan Shen
2021-06-15 17:32 ` [PATCH 19/27] arm64: dts: mt8195: add dp_intf node Tinghan Shen
2021-06-15 17:32 ` [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node Tinghan Shen
2021-06-15 17:32 ` [PATCH 21/27] arm64: dts: mt8195: add audio related nodes Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen [this message]
2021-06-15 23:30 ` [PATCH 22/27] arm64: dts: mt8195: add edp nodes Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 23/27] arm64: dts: mt8195: add gce node Tinghan Shen
2021-06-18 14:07 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node Tinghan Shen
2021-06-15 17:32 ` [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195 Tinghan Shen
2021-06-15 23:23 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 26/27] arm64: dts: mt8195: add scp device node Tinghan Shen
2021-06-15 17:32 ` [PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes Tinghan Shen
2021-06-18 14:21 ` arm64: dts: mt8195: Add Mediatek SoC MT8195 " Matthias Brugger
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