From: <gabriel.fernandez@foss.st.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Etienne Carriere <etienne.carriere@foss.st.com>,
Gabriel Fernandez <gabriel.fernandez@foss.st.com>,
<marex@denx.de>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [RESEND PATCH v3 05/11] clk: stm32mp1: move RCC reset controller into RCC clock driver
Date: Thu, 17 Jun 2021 07:18:08 +0200 [thread overview]
Message-ID: <20210617051814.12018-6-gabriel.fernandez@foss.st.com> (raw)
In-Reply-To: <20210617051814.12018-1-gabriel.fernandez@foss.st.com>
From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
drivers/clk/clk-stm32mp1.c | 157 ++++++++++++++++++++++++++++++++++---
1 file changed, 144 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e2e9331f1cba..6d3a36f81b2d 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@@ -2055,16 +2056,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
-struct stm32_clock_match_data {
+struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
+ u32 clear_offset;
};
-static struct stm32_clock_match_data stm32mp1_data = {
+static struct stm32_rcc_match_data stm32mp1_data = {
.cfg = stm32mp1_clock_cfg,
.num = ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
+ .clear_offset = RCC_CLR,
};
static const struct of_device_id stm32mp1_match_data[] = {
@@ -2100,23 +2103,122 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
}
-static int stm32_rcc_init(struct device *dev, void __iomem *base,
- const struct of_device_id *match_data)
+#define STM32_RESET_ID_MASK GENMASK(15, 0)
+
+struct stm32_reset_data {
+ /* reset lock */
+ spinlock_t lock;
+ struct reset_controller_dev rcdev;
+ void __iomem *membase;
+ u32 clear_offset;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
{
- struct clk_hw_onecell_data *clk_data;
- struct clk_hw **hws;
- const struct of_device_id *match;
- const struct stm32_clock_match_data *data;
- int err, n, max_binding;
+ return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
- match = of_match_node(match_data, dev_of_node(dev));
- if (!match) {
- dev_err(dev, "match data not found\n");
- return -ENODEV;
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+
+ if (data->clear_offset) {
+ void __iomem *addr;
+
+ addr = data->membase + (bank * reg_width);
+ if (!assert)
+ addr += data->clear_offset;
+
+ writel(BIT(offset), addr);
+
+ } else {
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + (bank * reg_width));
+
+ if (assert)
+ reg |= BIT(offset);
+ else
+ reg &= ~BIT(offset);
+
+ writel(reg, data->membase + (bank * reg_width));
+
+ spin_unlock_irqrestore(&data->lock, flags);
}
+ return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ u32 reg;
+
+ reg = readl(data->membase + (bank * reg_width));
+
+ return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+ .assert = stm32_reset_assert,
+ .deassert = stm32_reset_deassert,
+ .status = stm32_reset_status,
+};
+
+static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match)
+{
+ const struct stm32_rcc_match_data *data = match->data;
+ struct stm32_reset_data *reset_data = NULL;
+
data = match->data;
+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+ if (!reset_data)
+ return -ENOMEM;
+
+ reset_data->membase = base;
+ reset_data->rcdev.owner = THIS_MODULE;
+ reset_data->rcdev.ops = &stm32_reset_ops;
+ reset_data->rcdev.of_node = dev_of_node(dev);
+ reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
+ reset_data->clear_offset = data->clear_offset;
+
+ return reset_controller_register(&reset_data->rcdev);
+}
+
+static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match)
+{
+ const struct stm32_rcc_match_data *data = match->data;
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **hws;
+ int err, n, max_binding;
+
max_binding = data->maxbinding;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
@@ -2145,6 +2247,35 @@ static int stm32_rcc_init(struct device *dev, void __iomem *base,
return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
}
+static int stm32_rcc_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match_data)
+{
+ const struct of_device_id *match;
+ int err;
+
+ match = of_match_node(match_data, dev_of_node(dev));
+ if (!match) {
+ dev_err(dev, "match data not found\n");
+ return -ENODEV;
+ }
+
+ /* RCC Reset Configuration */
+ err = stm32_rcc_reset_init(dev, base, match);
+ if (err) {
+ pr_err("stm32mp1 reset failed to initialize\n");
+ return err;
+ }
+
+ /* RCC Clock Configuration */
+ err = stm32_rcc_clock_init(dev, base, match);
+ if (err) {
+ pr_err("stm32mp1 clock failed to initialize\n");
+ return err;
+ }
+
+ return 0;
+}
+
static int stm32mp1_rcc_init(struct device *dev)
{
void __iomem *base;
--
2.17.1
next prev parent reply other threads:[~2021-06-17 5:18 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 5:18 [RESEND PATCH v3 00/11] Introduce STM32MP1 RCC in secured mode gabriel.fernandez
2021-06-17 5:18 ` [RESEND PATCH v3 01/11] clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock gabriel.fernandez
2021-06-28 1:34 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 02/11] clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' " gabriel.fernandez
2021-06-28 1:34 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 03/11] clk: stm32mp1: remove intermediate pll clocks gabriel.fernandez
2021-06-28 1:35 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 04/11] clk: stm32mp1: convert to module driver gabriel.fernandez
2021-06-28 1:35 ` Stephen Boyd
2021-06-17 5:18 ` gabriel.fernandez [this message]
2021-06-28 1:35 ` [RESEND PATCH v3 05/11] clk: stm32mp1: move RCC reset controller into RCC clock driver Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 06/11] reset: stm32mp1: remove stm32mp1 reset gabriel.fernandez
2021-06-28 1:35 ` Stephen Boyd
2021-06-28 7:01 ` gabriel.fernandez
2021-06-28 7:17 ` Philipp Zabel
2021-06-17 5:18 ` [RESEND PATCH v3 07/11] dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 gabriel.fernandez
2021-06-28 1:35 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 08/11] dt-bindings: reset: add IDs for SCMI reset domains " gabriel.fernandez
2021-06-28 1:36 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 09/11] dt-bindings: reset: add MCU HOLD BOOT ID " gabriel.fernandez
2021-06-28 1:36 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 10/11] dt-bindings: clock: stm32mp1 new compatible for secure rcc gabriel.fernandez
2021-06-28 1:36 ` Stephen Boyd
2021-06-17 5:18 ` [RESEND PATCH v3 11/11] clk: stm32mp1: new compatible for secure RCC support gabriel.fernandez
2021-06-17 6:46 ` Marek Vasut
2021-06-18 13:24 ` gabriel.fernandez
2021-06-28 1:36 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210617051814.12018-6-gabriel.fernandez@foss.st.com \
--to=gabriel.fernandez@foss.st.com \
--cc=alexandre.torgue@foss.st.com \
--cc=devicetree@vger.kernel.org \
--cc=etienne.carriere@foss.st.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=marex@denx.de \
--cc=mcoquelin.stm32@gmail.com \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).