From: "tip-bot2 for Kan Liang" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Kan Liang <kan.liang@linux.intel.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Andi Kleen <ak@linux.intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: perf/core] perf/x86/intel/uncore: Add Sapphire Rapids server M2M support
Date: Mon, 05 Jul 2021 07:53:42 -0000 [thread overview]
Message-ID: <162547162273.395.16534832346812561443.tip-bot2@tip-bot2> (raw)
In-Reply-To: <1625087320-194204-9-git-send-email-kan.liang@linux.intel.com>
The following commit has been merged into the perf/core branch of tip:
Commit-ID: f57191edaaeb01279a88ace1be5b7230bdd8c0ab
Gitweb: https://git.kernel.org/tip/f57191edaaeb01279a88ace1be5b7230bdd8c0ab
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Wed, 30 Jun 2021 14:08:32 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 02 Jul 2021 15:58:39 +02:00
perf/x86/intel/uncore: Add Sapphire Rapids server M2M support
The M2M blocks manage the interface between the mesh (operating on both
the mesh and the SMI3 protocol) and the memory controllers.
The layout of the control registers for a M2M uncore unit is a little
bit different from the generic one. So a specific format and ops are
required. Expose the common PCI ops which can be reused.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-9-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/uncore_discovery.c | 14 +++++------
arch/x86/events/intel/uncore_discovery.h | 8 ++++++-
arch/x86/events/intel/uncore_snbep.c | 30 ++++++++++++++++++++++-
3 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c
index cc44311..6322df1 100644
--- a/arch/x86/events/intel/uncore_discovery.c
+++ b/arch/x86/events/intel/uncore_discovery.c
@@ -377,7 +377,7 @@ static struct intel_uncore_ops generic_uncore_msr_ops = {
.read_counter = uncore_msr_read_counter,
};
-static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -386,7 +386,7 @@ static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
}
-static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -394,7 +394,7 @@ static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
}
-static void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -411,8 +411,8 @@ static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,
pci_write_config_dword(pdev, hwc->config_base, hwc->config);
}
-static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
- struct perf_event *event)
+void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
+ struct perf_event *event)
{
struct pci_dev *pdev = box->pci_dev;
struct hw_perf_event *hwc = &event->hw;
@@ -420,8 +420,8 @@ static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
pci_write_config_dword(pdev, hwc->config_base, 0);
}
-static u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
- struct perf_event *event)
+u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
+ struct perf_event *event)
{
struct pci_dev *pdev = box->pci_dev;
struct hw_perf_event *hwc = &event->hw;
diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/intel/uncore_discovery.h
index 9723243..b85655b 100644
--- a/arch/x86/events/intel/uncore_discovery.h
+++ b/arch/x86/events/intel/uncore_discovery.h
@@ -140,5 +140,13 @@ void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
struct perf_event *event);
+void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
+ struct perf_event *event);
+u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
+ struct perf_event *event);
+
struct intel_uncore_type **
intel_uncore_generic_init_uncores(enum uncore_access_type type_id);
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 3c9d459..72ba8d4 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5670,6 +5670,34 @@ static struct intel_uncore_type spr_uncore_imc = {
.ops = &spr_uncore_mmio_ops,
};
+static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,
+ struct perf_event *event)
+{
+ struct pci_dev *pdev = box->pci_dev;
+ struct hw_perf_event *hwc = &event->hw;
+
+ pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32));
+ pci_write_config_dword(pdev, hwc->config_base, (u32)hwc->config);
+}
+
+static struct intel_uncore_ops spr_uncore_pci_ops = {
+ .init_box = intel_generic_uncore_pci_init_box,
+ .disable_box = intel_generic_uncore_pci_disable_box,
+ .enable_box = intel_generic_uncore_pci_enable_box,
+ .disable_event = intel_generic_uncore_pci_disable_event,
+ .enable_event = spr_uncore_pci_enable_event,
+ .read_counter = intel_generic_uncore_pci_read_counter,
+};
+
+#define SPR_UNCORE_PCI_COMMON_FORMAT() \
+ SPR_UNCORE_COMMON_FORMAT(), \
+ .ops = &spr_uncore_pci_ops
+
+static struct intel_uncore_type spr_uncore_m2m = {
+ SPR_UNCORE_PCI_COMMON_FORMAT(),
+ .name = "m2m",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5680,7 +5708,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_pcu,
NULL,
&spr_uncore_imc,
- NULL,
+ &spr_uncore_m2m,
NULL,
NULL,
NULL,
next prev parent reply other threads:[~2021-07-05 7:53 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-30 21:08 [PATCH V4 00/16] perf: Add Sapphire Rapids server uncore support kan.liang
2021-06-30 21:08 ` [PATCH V4 01/16] perf/x86/intel/uncore: Add Sapphire Rapids server framework kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 02/16] perf/x86/intel/uncore: Add Sapphire Rapids server CHA support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 03/16] perf/x86/intel/uncore: Add Sapphire Rapids server IIO support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 04/16] perf/x86/intel/uncore: Add Sapphire Rapids server IRP support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 05/16] perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 06/16] perf/x86/intel/uncore: Add Sapphire Rapids server PCU support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 07/16] perf/x86/intel/uncore: Add Sapphire Rapids server IMC support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 08/16] perf/x86/intel/uncore: Add Sapphire Rapids server M2M support kan.liang
2021-07-05 7:53 ` tip-bot2 for Kan Liang [this message]
2021-06-30 21:08 ` [PATCH V4 09/16] perf/x86/intel/uncore: Add Sapphire Rapids server UPI support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 10/16] perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 11/16] perf/x86/intel/uncore: Add Sapphire Rapids server MDF support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 12/16] perf/x86/intel/uncore: Add alias PMU name kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 13/16] perf/x86/intel/uncore: Factor out snr_uncore_mmio_map() kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 14/16] perf/x86/intel/uncore: Support IIO free-running counters on Sapphire Rapids server kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 15/16] perf/x86/intel/uncore: Support IMC " kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 16/16] perf pmu: Add PMU alias support kan.liang
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