From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linuxarm@huawei.com, mauro.chehab@huawei.com,
Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Xiaowei Song <songxiaowei@hisilicon.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH v4 4/8] dt-bindings: PCI: kirin: Drop PHY properties
Date: Mon, 12 Jul 2021 23:46:42 +0200 [thread overview]
Message-ID: <a04c9c92187ceaee0fd4b8d4721e2a3275d97518.1626126198.git.mchehab+huawei@kernel.org> (raw)
In-Reply-To: <cover.1626126198.git.mchehab+huawei@kernel.org>
There are several properties there that belong to the PHY
interface. Drop them, as a new binding file will describe
the PHY properties for Kirin 960.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
index 71cac2b74002..a93a8cfa1afb 100644
--- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -10,13 +10,11 @@ Additional properties are described here:
Required properties
- compatible:
"hisilicon,kirin960-pcie"
-- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg: Should contain rc_dbi, apb, config registers location and length.
- reg-names: Must include the following entries:
"dbi": controller configuration registers;
"apb": apb Ctrl register defined by Kirin;
- "phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
-- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
@@ -25,8 +23,8 @@ Example based on kirin960:
pcie@f4000000 {
compatible = "hisilicon,kirin960-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
- <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
- reg-names = "dbi","apb","phy", "config";
+ <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
@@ -39,12 +37,4 @@ Example based on kirin960:
<0x0 0 0 2 &gic 0 0 0 283 4>,
<0x0 0 0 3 &gic 0 0 0 284 4>,
<0x0 0 0 4 &gic 0 0 0 285 4>;
- clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
- <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
- <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
- clock-names = "pcie_phy_ref", "pcie_aux",
- "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
- reset-gpios = <&gpio11 1 0 >;
};
--
2.31.1
next prev parent reply other threads:[~2021-07-12 21:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-12 21:46 [PATCH v4 0/8] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 1/8] dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 2/8] dt-bindings: phy: Add bindings for HiKey 970 " Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 3/8] dt-bindings: PCI: kirin: Fix compatible string Mauro Carvalho Chehab
2021-07-12 21:46 ` Mauro Carvalho Chehab [this message]
2021-07-12 21:46 ` [PATCH v4 5/8] phy: HiSilicon: Add driver for Kirin 960 PCIe PHY Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 6/8] phy: HiSilicon: add driver for Kirin 970 " Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 7/8] PCI: kirin: Drop the PHY logic from the driver Mauro Carvalho Chehab
2021-07-12 21:46 ` [PATCH v4 8/8] PCI: kirin: Use regmap for APB registers Mauro Carvalho Chehab
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