From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>, Christoph Hellwig <hch@lst.de>,
devicetree@vger.kernel.org, Dmitry Vyukov <dvyukov@google.com>,
Frank Rowand <frowand.list@gmail.com>,
Guo Ren <guoren@linux.alibaba.com>,
iommu@lists.linux-foundation.org,
linux-riscv@lists.infradead.org,
Marek Szyprowski <m.szyprowski@samsung.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Tobias Klauser <tklauser@distanz.ch>
Subject: [RFC 1/5] RISC-V: Implement arch_sync_dma* functions
Date: Fri, 23 Jul 2021 14:40:27 -0700 [thread overview]
Message-ID: <20210723214031.3251801-2-atish.patra@wdc.com> (raw)
In-Reply-To: <20210723214031.3251801-1-atish.patra@wdc.com>
To facilitate streaming DMA APIs, this patch introduces a set of generic
cache operations related dma sync. Any platform can use the generic ops
to provide platform specific cache management operations. Once the
standard RISC-V CMO extension is available, it can be built on top of it.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/dma-noncoherent.h | 19 +++++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/dma-noncoherent.c | 66 ++++++++++++++++++++++++
3 files changed, 86 insertions(+)
create mode 100644 arch/riscv/include/asm/dma-noncoherent.h
create mode 100644 arch/riscv/mm/dma-noncoherent.c
diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h
new file mode 100644
index 000000000000..5bdb03c9c427
--- /dev/null
+++ b/arch/riscv/include/asm/dma-noncoherent.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#ifndef __ASM_RISCV_DMA_NON_COHERENT_H
+#define __ASM_RISCV_DMA_NON_COHERENT_H
+
+#ifdef CONFIG_RISCV_DMA_NONCOHERENT
+struct riscv_dma_cache_sync {
+ void (*cache_invalidate)(phys_addr_t paddr, size_t size);
+ void (*cache_clean)(phys_addr_t paddr, size_t size);
+ void (*cache_flush)(phys_addr_t paddr, size_t size);
+};
+
+void riscv_dma_cache_sync_set(struct riscv_dma_cache_sync *ops);
+#endif
+
+#endif
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 7ebaef10ea1b..959bef49098b 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -27,3 +27,4 @@ KASAN_SANITIZE_init.o := n
endif
obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
+obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
new file mode 100644
index 000000000000..2f6e9627c4aa
--- /dev/null
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RISC-V specific functions to support DMA for non-coherent devices
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/dma-direct.h>
+#include <linux/dma-map-ops.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <asm/dma-noncoherent.h>
+
+static struct riscv_dma_cache_sync *dma_cache_sync;
+unsigned long riscv_dma_uc_offset;
+
+static void __dma_sync(phys_addr_t paddr, size_t size, enum dma_data_direction dir)
+{
+ if ((dir == DMA_FROM_DEVICE) && (dma_cache_sync->cache_invalidate))
+ dma_cache_sync->cache_invalidate(paddr, size);
+ else if ((dir == DMA_TO_DEVICE) && (dma_cache_sync->cache_clean))
+ dma_cache_sync->cache_clean(paddr, size);
+ else if ((dir == DMA_BIDIRECTIONAL) && dma_cache_sync->cache_flush)
+ dma_cache_sync->cache_flush(paddr, size);
+}
+
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir)
+{
+ if (!dma_cache_sync)
+ return;
+
+ __dma_sync(paddr, size, dir);
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, enum dma_data_direction dir)
+{
+ if (!dma_cache_sync)
+ return;
+
+ __dma_sync(paddr, size, dir);
+}
+
+void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+ const struct iommu_ops *iommu, bool coherent)
+{
+ /* If a specific device is dma-coherent, set it here */
+ dev->dma_coherent = coherent;
+}
+
+void arch_dma_prep_coherent(struct page *page, size_t size)
+{
+ void *flush_addr = page_address(page);
+
+ memset(flush_addr, 0, size);
+ if (dma_cache_sync && dma_cache_sync->cache_flush)
+ dma_cache_sync->cache_flush(__pa(flush_addr), size);
+}
+
+void riscv_dma_cache_sync_set(struct riscv_dma_cache_sync *ops)
+{
+ dma_cache_sync = ops;
+}
--
2.31.1
next prev parent reply other threads:[~2021-07-23 21:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 21:40 [RFC 0/5] Support non-coherent DMA on RISC-V using a global pool Atish Patra
2021-07-23 21:40 ` Atish Patra [this message]
2021-07-26 6:56 ` [RFC 1/5] RISC-V: Implement arch_sync_dma* functions Christoph Hellwig
2021-07-26 21:52 ` Atish Patra
2021-09-11 9:37 ` Guo Ren
2021-08-17 1:48 ` Guo Ren
2021-08-17 3:24 ` Atish Patra
2021-08-17 6:28 ` Guo Ren
2021-07-23 21:40 ` [RFC 2/5] of: Move of_dma_get_range to of_address.h Atish Patra
2021-07-23 21:40 ` [RFC 3/5] dma-mapping: Enable global non-coherent pool support for RISC-V Atish Patra
2021-07-25 22:29 ` Rob Herring
2021-07-26 7:00 ` Christoph Hellwig
2021-07-26 22:47 ` Atish Patra
2021-07-27 8:52 ` Christoph Hellwig
2021-08-02 18:22 ` Atish Patra
2021-07-23 21:40 ` [RFC 4/5] dma-direct: Allocate dma pages directly if global pool allocation fails Atish Patra
2021-07-26 7:01 ` Christoph Hellwig
2021-07-23 21:40 ` [RFC 5/5] RISC-V: Support a new config option for non-coherent DMA Atish Patra
2021-07-29 4:30 ` [RFC 0/5] Support non-coherent DMA on RISC-V using a global pool Palmer Dabbelt
2021-07-29 6:19 ` Atish Patra
2021-08-17 1:37 ` Guo Ren
2021-08-17 3:28 ` Atish Patra
2021-08-17 6:42 ` Guo Ren
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