From: Rob Clark <robdclark@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: "Daniel Vetter" <daniel@ffwll.ch>,
"Matthew Brost" <matthew.brost@intel.com>,
"Michel Dänzer" <michel@daenzer.net>,
"Christian König" <ckoenig.leichtzumerken@gmail.com>,
"Rob Clark" <robdclark@chromium.org>,
"Rob Clark" <robdclark@gmail.com>, "Sean Paul" <sean@poorly.run>,
"David Airlie" <airlied@linux.ie>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM
ADRENO GPU),
freedreno@lists.freedesktop.org (open list:DRM DRIVER FOR MSM
ADRENO GPU), linux-kernel@vger.kernel.org (open list),
linux-media@vger.kernel.org (open list:DMA BUFFER SHARING
FRAMEWORK),
linaro-mm-sig@lists.linaro.org (moderated list:DMA BUFFER
SHARING FRAMEWORK)
Subject: [RFC 5/4] drm/msm: Add deadline based boost support
Date: Tue, 27 Jul 2021 14:17:33 -0700 [thread overview]
Message-ID: <20210727211733.2601469-1-robdclark@gmail.com> (raw)
In-Reply-To: <20210726233854.2453899-1-robdclark@gmail.com>
From: Rob Clark <robdclark@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
This is a quick implementation of what I had in mind for driver side
of deadline boost. For a couple games with bad gpu devfreq behavior
this boosts "Render quality" from ~35% to ~95%. (The "Render quality"
metric in chrome://arc-overview-tracing is basically a measure of the
deviation in frame/commit time, so 100% would be a consistent fps
with no variantion.) Not quite 100%, this is still a bit of a re-
active mechanism.
A similar result can be had by tuning devfreq to boost to max OPP at
a much lower threshold of busyness. With the obvious downside that
you spend a lot of time running the GPU much faster than needed.
drivers/gpu/drm/msm/msm_fence.c | 76 +++++++++++++++++++++++++++
drivers/gpu/drm/msm/msm_fence.h | 20 +++++++
drivers/gpu/drm/msm/msm_gpu.h | 1 +
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++++++
4 files changed, 117 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
index f2cece542c3f..67c2a96e1c85 100644
--- a/drivers/gpu/drm/msm/msm_fence.c
+++ b/drivers/gpu/drm/msm/msm_fence.c
@@ -8,6 +8,37 @@
#include "msm_drv.h"
#include "msm_fence.h"
+#include "msm_gpu.h"
+
+static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence);
+
+static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx)
+{
+ struct msm_drm_private *priv = fctx->dev->dev_private;
+ return priv->gpu;
+}
+
+static enum hrtimer_restart deadline_timer(struct hrtimer *t)
+{
+ struct msm_fence_context *fctx = container_of(t,
+ struct msm_fence_context, deadline_timer);
+
+ kthread_queue_work(fctx2gpu(fctx)->worker, &fctx->deadline_work);
+
+ return HRTIMER_NORESTART;
+}
+
+static void deadline_work(struct kthread_work *work)
+{
+ struct msm_fence_context *fctx = container_of(work,
+ struct msm_fence_context, deadline_work);
+
+ /* If deadline fence has already passed, nothing to do: */
+ if (fence_completed(fctx, fctx->next_deadline_fence))
+ return;
+
+ msm_devfreq_boost(fctx2gpu(fctx), 2);
+}
struct msm_fence_context *
@@ -26,6 +57,13 @@ msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr,
fctx->fenceptr = fenceptr;
spin_lock_init(&fctx->spinlock);
+ hrtimer_init(&fctx->deadline_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+ fctx->deadline_timer.function = deadline_timer;
+
+ kthread_init_work(&fctx->deadline_work, deadline_work);
+
+ fctx->next_deadline = ktime_get();
+
return fctx;
}
@@ -49,6 +87,8 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
{
spin_lock(&fctx->spinlock);
fctx->completed_fence = max(fence, fctx->completed_fence);
+ if (fence_completed(fctx, fctx->next_deadline_fence))
+ hrtimer_cancel(&fctx->deadline_timer);
spin_unlock(&fctx->spinlock);
}
@@ -79,10 +119,46 @@ static bool msm_fence_signaled(struct dma_fence *fence)
return fence_completed(f->fctx, f->base.seqno);
}
+static void msm_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
+{
+ struct msm_fence *f = to_msm_fence(fence);
+ struct msm_fence_context *fctx = f->fctx;
+ unsigned long flags;
+ ktime_t now;
+
+ spin_lock_irqsave(&fctx->spinlock, flags);
+ now = ktime_get();
+
+ if (ktime_after(now, fctx->next_deadline) ||
+ ktime_before(deadline, fctx->next_deadline)) {
+ fctx->next_deadline = deadline;
+ fctx->next_deadline_fence =
+ max(fctx->next_deadline_fence, (uint32_t)fence->seqno);
+
+ /*
+ * Set timer to trigger boost 3ms before deadline, or
+ * if we are already less than 3ms before the deadline
+ * schedule boost work immediately.
+ */
+ deadline = ktime_sub(deadline, ms_to_ktime(3));
+
+ if (ktime_after(now, deadline)) {
+ kthread_queue_work(fctx2gpu(fctx)->worker,
+ &fctx->deadline_work);
+ } else {
+ hrtimer_start(&fctx->deadline_timer, deadline,
+ HRTIMER_MODE_ABS);
+ }
+ }
+
+ spin_unlock_irqrestore(&fctx->spinlock, flags);
+}
+
static const struct dma_fence_ops msm_fence_ops = {
.get_driver_name = msm_fence_get_driver_name,
.get_timeline_name = msm_fence_get_timeline_name,
.signaled = msm_fence_signaled,
+ .set_deadline = msm_fence_set_deadline,
};
struct dma_fence *
diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h
index 4783db528bcc..d34e853c555a 100644
--- a/drivers/gpu/drm/msm/msm_fence.h
+++ b/drivers/gpu/drm/msm/msm_fence.h
@@ -50,6 +50,26 @@ struct msm_fence_context {
volatile uint32_t *fenceptr;
spinlock_t spinlock;
+
+ /*
+ * TODO this doesn't really deal with multiple deadlines, like
+ * if userspace got multiple frames ahead.. OTOH atomic updates
+ * don't queue, so maybe that is ok
+ */
+
+ /** next_deadline: Time of next deadline */
+ ktime_t next_deadline;
+
+ /**
+ * next_deadline_fence:
+ *
+ * Fence value for next pending deadline. The deadline timer is
+ * canceled when this fence is signaled.
+ */
+ uint32_t next_deadline_fence;
+
+ struct hrtimer deadline_timer;
+ struct kthread_work deadline_work;
};
struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 0e4b45bff2e6..e031c9b495ed 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -425,6 +425,7 @@ void msm_devfreq_init(struct msm_gpu *gpu);
void msm_devfreq_cleanup(struct msm_gpu *gpu);
void msm_devfreq_resume(struct msm_gpu *gpu);
void msm_devfreq_suspend(struct msm_gpu *gpu);
+void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
void msm_devfreq_active(struct msm_gpu *gpu);
void msm_devfreq_idle(struct msm_gpu *gpu);
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 0a1ee20296a2..8a8d7b9028a3 100644
--- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -144,6 +144,26 @@ void msm_devfreq_suspend(struct msm_gpu *gpu)
devfreq_suspend_device(gpu->devfreq.devfreq);
}
+void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor)
+{
+ struct msm_gpu_devfreq *df = &gpu->devfreq;
+ unsigned long freq;
+
+ /*
+ * Hold devfreq lock to synchronize with get_dev_status()/
+ * target() callbacks
+ */
+ mutex_lock(&df->devfreq->lock);
+
+ freq = get_freq(gpu);
+
+ freq *= factor;
+
+ msm_devfreq_target(&gpu->pdev->dev, &freq, 0);
+
+ mutex_unlock(&df->devfreq->lock);
+}
+
void msm_devfreq_active(struct msm_gpu *gpu)
{
struct msm_gpu_devfreq *df = &gpu->devfreq;
--
2.31.1
prev parent reply other threads:[~2021-07-27 21:13 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-26 23:38 [RFC 0/4] dma-fence: Deadline awareness Rob Clark
2021-07-26 23:38 ` [RFC 1/4] dma-fence: Add deadline awareness Rob Clark
2021-07-27 7:11 ` Christian König
2021-07-27 14:25 ` Rob Clark
2021-07-28 7:03 ` Christian König
2021-07-28 11:37 ` Christian König
2021-07-28 15:15 ` Rob Clark
2021-07-28 17:23 ` Christian König
2021-07-28 17:58 ` Rob Clark
2021-07-29 7:03 ` Daniel Vetter
2021-07-29 15:23 ` Rob Clark
2021-07-29 16:18 ` Daniel Vetter
2021-07-29 17:32 ` Rob Clark
2021-07-26 23:38 ` [RFC 2/4] drm/vblank: Add helper to get next vblank time Rob Clark
2021-07-26 23:38 ` [RFC 3/4] drm/atomic-helper: Set fence deadline for vblank Rob Clark
2021-07-27 10:44 ` Michel Dänzer
2021-07-27 14:33 ` Rob Clark
2021-07-26 23:38 ` [RFC 4/4] drm/scheduler: Add fence deadline support Rob Clark
2021-07-26 23:51 ` [RFC 0/4] dma-fence: Deadline awareness Rob Clark
2021-07-27 14:41 ` Michel Dänzer
2021-07-27 15:12 ` Rob Clark
2021-07-27 15:19 ` Michel Dänzer
2021-07-27 15:37 ` Rob Clark
2021-07-28 11:36 ` Christian König
2021-07-28 13:08 ` Michel Dänzer
2021-07-28 13:13 ` Christian König
2021-07-28 13:24 ` Michel Dänzer
2021-07-28 13:31 ` Christian König
2021-07-28 13:57 ` Pekka Paalanen
2021-07-28 14:30 ` Christian König
2021-07-29 8:08 ` Michel Dänzer
2021-07-29 8:23 ` Pekka Paalanen
2021-07-29 8:43 ` Christian König
2021-07-29 9:15 ` Pekka Paalanen
2021-07-29 10:14 ` Christian König
2021-07-29 10:28 ` Michel Dänzer
2021-07-29 11:00 ` Pekka Paalanen
2021-07-29 11:43 ` Christian König
2021-07-29 12:49 ` Pekka Paalanen
2021-07-29 13:41 ` Christian König
2021-07-29 14:10 ` Pekka Paalanen
2021-07-28 15:27 ` Rob Clark
2021-07-28 17:20 ` Christian König
2021-07-28 15:34 ` Rob Clark
2021-07-29 7:09 ` Daniel Vetter
2021-07-29 8:17 ` Michel Dänzer
2021-07-29 9:03 ` Daniel Vetter
2021-07-29 9:37 ` Pekka Paalanen
2021-07-29 12:18 ` Daniel Vetter
2021-07-29 12:59 ` Pekka Paalanen
2021-07-29 14:05 ` Daniel Vetter
2021-07-27 21:17 ` Rob Clark [this message]
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