From: Rajendra Nayak <rnayak@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
srinivas.kandagatla@linaro.org, robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, rbokka@codeaurora.org,
dianders@chromium.org, Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH v3 3/4] nvmem: qfprom: sc7280: Handle the additional power-domains vote
Date: Fri, 30 Jul 2021 12:16:12 +0530 [thread overview]
Message-ID: <1627627573-32454-4-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1627627573-32454-1-git-send-email-rnayak@codeaurora.org>
On sc7280, to reliably blow fuses, we need an additional vote
on max performance state of 'MX' power-domain.
Add support for power-domain performance state voting in the
driver.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
drivers/nvmem/qfprom.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index b0ca4c6..c500d62 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -12,6 +12,8 @@
#include <linux/mod_devicetable.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
@@ -142,6 +144,9 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
+ dev_pm_genpd_set_performance_state(priv->dev, 0);
+ pm_runtime_put(priv->dev);
+
/*
* This may be a shared rail and may be able to run at a lower rate
* when we're not blowing fuses. At the moment, the regulator framework
@@ -212,6 +217,14 @@ static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
goto err_clk_rate_set;
}
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(priv->dev);
+ dev_err(priv->dev, "Failed to enable power-domain\n");
+ goto err_reg_enable;
+ }
+ dev_pm_genpd_set_performance_state(priv->dev, INT_MAX);
+
old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
writel(priv->soc_data->qfprom_blow_timer_value,
@@ -221,6 +234,8 @@ static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
return 0;
+err_reg_enable:
+ regulator_disable(priv->vcc);
err_clk_rate_set:
clk_set_rate(priv->secclk, old->clk_rate);
err_clk_prepared:
@@ -320,6 +335,11 @@ static int qfprom_reg_read(void *context,
return 0;
}
+static void qfprom_runtime_disable(void *data)
+{
+ pm_runtime_disable(data);
+}
+
static const struct qfprom_soc_data qfprom_7_8_data = {
.accel_value = 0xD10,
.qfprom_blow_timer_value = 25,
@@ -420,6 +440,11 @@ static int qfprom_probe(struct platform_device *pdev)
econfig.reg_write = qfprom_reg_write;
}
+ pm_runtime_enable(dev);
+ ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
+ if (ret)
+ return ret;
+
nvmem = devm_nvmem_register(dev, &econfig);
return PTR_ERR_OR_ZERO(nvmem);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-07-30 6:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-30 6:46 [PATCH v3 0/4] nvmem: qfprom: Add binding updates and power-domain handling Rajendra Nayak
2021-07-30 6:46 ` [PATCH v3 1/4] dt-bindings: nvmem: qfprom: Add optional power-domains property Rajendra Nayak
2021-08-03 19:38 ` Rob Herring
2021-07-30 6:46 ` [PATCH v3 2/4] nvmem: qfprom: Fix up qfprom_disable_fuse_blowing() ordering Rajendra Nayak
2021-07-30 13:49 ` Doug Anderson
2021-07-30 6:46 ` Rajendra Nayak [this message]
2021-07-30 6:46 ` [PATCH v3 4/4] arm64: dts: qcom: sc7280: Add qfprom node Rajendra Nayak
2021-08-04 8:29 ` [PATCH v3 0/4] nvmem: qfprom: Add binding updates and power-domain handling Srinivas Kandagatla
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