From: "tip-bot2 for Like Xu" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Like Xu <likexu@tencent.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Liam Merwick <liam.merwick@oracle.com>,
Kim Phillips <kim.phillips@amd.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: perf/urgent] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
Date: Thu, 05 Aug 2021 09:34:28 -0000 [thread overview]
Message-ID: <162815606869.395.8997137741272927624.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20210802070850.35295-1-likexu@tencent.com>
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27
Gitweb: https://git.kernel.org/tip/df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27
Author: Like Xu <likexu@tencent.com>
AuthorDate: Mon, 02 Aug 2021 15:08:50 +08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 04 Aug 2021 15:16:34 +02:00
perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
[] Call Trace:
[] amd_pmu_disable_event+0x22/0x90
[] x86_pmu_stop+0x4c/0xa0
[] x86_pmu_del+0x3a/0x140
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
while the guest perf driver should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Liam Merwick <liam.merwick@oracle.com>
Tested-by: Kim Phillips <kim.phillips@amd.com>
Tested-by: Liam Merwick <liam.merwick@oracle.com>
Link: https://lkml.kernel.org/r/20210802070850.35295-1-likexu@tencent.com
---
arch/x86/events/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2bf1c7e..2938c90 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1115,9 +1115,10 @@ void x86_pmu_stop(struct perf_event *event, int flags);
static inline void x86_pmu_disable_event(struct perf_event *event)
{
+ u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
struct hw_perf_event *hwc = &event->hw;
- wrmsrl(hwc->config_base, hwc->config);
+ wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
if (is_counter_pair(hwc))
wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
prev parent reply other threads:[~2021-08-05 9:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 7:08 [PATCH v2] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest Like Xu
2021-08-04 11:28 ` Liam Merwick
2021-08-04 13:02 ` Peter Zijlstra
2021-08-05 9:34 ` tip-bot2 for Like Xu [this message]
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