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From: Richard Fitzgerald <rf@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: <alsa-devel@alsa-project.org>, <patches@opensource.cirrus.com>,
	<linux-kernel@vger.kernel.org>,
	Richard Fitzgerald <rf@opensource.cirrus.com>
Subject: [PATCH 8/8] ASoC: cs42l42: Update module authors
Date: Thu, 5 Aug 2021 17:11:11 +0100	[thread overview]
Message-ID: <20210805161111.10410-8-rf@opensource.cirrus.com> (raw)
In-Reply-To: <20210805161111.10410-1-rf@opensource.cirrus.com>

Add the current authors of this module.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
---
 sound/soc/codecs/cs42l42.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 3677ed4670d0..fb1e4c33e27d 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -2127,4 +2127,7 @@ MODULE_DESCRIPTION("ASoC CS42L42 driver");
 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
+MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
 MODULE_LICENSE("GPL");
-- 
2.11.0


  parent reply	other threads:[~2021-08-05 16:11 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-05 16:11 [PATCH 1/8] ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 2/8] ASoC: cs42l42: Fix LRCLK frame start edge Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 3/8] ASoC: cs42l42: Constrain sample rate to prevent illegal SCLK Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 4/8] ASoC: cs42l42: Fix mono playback Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 5/8] ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 6/8] ASoC: cs42l42: Validate dai_set_sysclk() frequency Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 7/8] ASoC: cs42l42: Assume 24-bit samples are in 32-bit slots Richard Fitzgerald
2021-08-05 16:11 ` Richard Fitzgerald [this message]
2021-08-06  0:45 ` [PATCH 1/8] ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL Mark Brown
2021-08-06  0:47 ` Mark Brown
2021-08-06  0:56 ` Mark Brown

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