From: Stephane Eranian <eranian@google.com>
To: linux-kernel@vger.kernel.org
Cc: peterz@infradead.org, mingo@elte.hu, paulus@samba.org,
davem@davemloft.net, fweisbec@gmail.com,
perfmon2-devel@lists.sf.net, eranian@gmail.com,
eranian@google.com
Subject: [PATCH] perf_events: update Intel Westmere event constraints
Date: Thu, 10 Jun 2010 13:25:01 +0200 [thread overview]
Message-ID: <4c10cb56.5120e30a.2eb4.ffffc3de@mx.google.com> (raw)
Based on Intel Vol3b (March 2010), the event SNOOPQ_REQUEST_OUTSTANDING
is restricted to counters 0,1 so update the event table for Intel Westmere
accordingly.
Signed-off-by: Stephane Eranian <eranian@google.com>
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index fdbc652..1f51d7f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -72,6 +72,7 @@ static struct event_constraint intel_westmere_event_constraints[] =
INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
+ INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
EVENT_CONSTRAINT_END
};
next reply other threads:[~2010-06-10 11:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-10 11:25 Stephane Eranian [this message]
2010-06-10 12:25 ` [tip:perf/urgent] perf_events: Fix Intel Westmere event constraints tip-bot for Stephane Eranian
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